X9428
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
I
V
supply current
1
mA
f = 400kHz, SDA = Open,
SCL
CC1
CC
(nonvolatile write)
Other Inputs = V
SS
I
V
supply current
100
µA
f
= 400kHz, SDA = Open,
CC2
CC
(move wiper, write, read)
SCL
Other Inputs = V
SS
I
V
current (standby)
1
µA
µA
µA
V
SCL = SDA = V , Addr. = V
CC SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS
LI
IN
CC
CC
I
= V to V
SS
LO
OUT
V
V
x 0.7
V
V
x 0.5
IH
CC
-0.5
CC
V
x 0.1
V
IL
CC
V
0.4
V
I
= 3mA
OL
OL
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-
eter. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R - R )/63, single pot
H
L
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
(5)
C
Input/output capacitance (SDA)
8
6
V
= 0V
= 0V
I/O
I/O
(5)
C
Input capacitance (A0, A1, A2, A3, and SCL)
pF
V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Typ.
Max.
1
Unit
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
ms
ms
PUR
(6)
(7)
t
5
PUW
t V
V
Power-up ramp rate
CC
0.2
50
V/msec
R CC
POWER-UP AND POWER-DOWN
There are no restrictions on the power-up or power-down sequencing of the bias supplies V , V+, and V- provided
CC
that all three supplies reach their final values within 1msec of each other. However, at all times, the voltages on the
potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory
is not in effect until all supplies reach their final value.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) t
and t
are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific
PUR
PUW CC
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
FN8197.1
April 26, 2006
14
INTERSIL [ Intersil ]
