X9400
A.C. TEST CONDITIONS
SYMBOL TABLE
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
10ns
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing level
V
CC
Must be
steady
Will be
steady
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) t and t are the delays required from the time the
May change
from Low to
High
Will change
from Low to
High
PUR PUW
third (last) power supply (V , V+ or V-) is stable until the
CC
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
May change
from High to
Low
Will change
from High to
Low
SPICE Macro Model
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
R
TOTAL
N/A
Center Line
is High
Impedance
R
R
L
H
C
L
C
H
C
W
10pF
10pF
25pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
SCK
t
500
200
200
250
250
50
CYC
t
WH
t
WL
t
LEAD
t
Lag time
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
SU
t
50
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO output valid time
V
t
SO output hold time
HO
RO
t
SO output rise time
50
50
t
SO output fall time
FO
t
HOLD time
400
100
100
HOLD
t
HOLD setup time
HSU
t
HOLD hold time
HH
t
HOLD low to output in High Z
HOLD high to output in Low Z
100
100
20
HZ
t
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
I
t
2
0
0
CS
WPASU
t
WP, A0 and A1 setup time
t
WP, A0 and A1 hold time
WPAH
FN8189.3
July 28, 2006
13
INTERSIL [ Intersil ]
