X9258
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
Figure 8. Detailed Potentiometer Block Diagram Detailed Operation
Serial Data Path
V /R
H H
Serial
BUS
Input
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
Register 3
8
8
Parallel
BUS
Input
e
r
Wiper
D
e
c
Counter
Register
(WCR)
o
d
e
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = FF[H] then V /R = V /R
H
W
W
H
V /R
L
L
Modified SCL
CLK
V
/R
W
W
All DCP potentiometers share the serial interface and
share a common architecture. Each potentiometer has
a Wiper Counter Register and four Data Registers. A
detailed discussion of the register organization and
array operation follows.
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (R0) upon power-up.
Wiper Counter Register
The X9258 contains four Wiper Counter Registers,
one for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
FN8168.1
7
May 6, 2005
INTERSIL [ Intersil ]
