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X9258US24I 参数 Datasheet PDF下载

X9258US24I图片预览
型号: X9258US24I
PDF下载: 下载PDF文件 查看货源
内容描述: 低噪音/低功耗/ 2 - Wire总线/ 256水龙头 [Low Noise/Low Power/2-Wire Bus/256 Taps]
分类和应用: 转换器电阻器光电二极管
文件页数/大小: 20 页 / 347 K
品牌: INTERSIL [ Intersil ]
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X9258  
and provide the clock for both transmit and receive  
operations. Therefore, the X9258 will be considered a  
slave device in all applications.  
The WCR may be written directly, or it can be changed  
by transferring the contents of one of four associated  
data registers into the WCR. These data registers and  
the WCR can be read and written by the host system.  
Clock and Data Conventions  
Device Addressing  
Data states on the SDA line can change only during  
SCL LOW periods (t  
SCL HIGH are reserved for indicating start and stop  
conditions.  
). SDA state changes during  
Following a start condition the master must output the  
address of the slave it is accessing. The most  
significant four bits of the slave address are the device  
type identifier (refer to Figure 1 below). For the X9258  
this is fixed as 0101[B].  
LOW  
Start Condition  
All commands to the X9258 are preceded by the start  
condition, which is a HIGH to LOW transition of SDA  
Figure 1. Slave Address  
while SCL is HIGH (t  
). The X9258 continuously  
HIGH  
Device Type  
Identifier  
monitors the SDA and SCL lines for the start condition  
and will not respond to any command until this  
condition is met.  
0
1
0
1
A3  
A2  
A1  
A0  
Stop Condition  
All communications must be terminated by a stop  
condition, which is a LOW to HIGH transition of SDA  
while SCL is HIGH.  
Device Address  
The next four bits of the slave address are the device  
address. The physical device address is defined by the  
state of the A0 - A3 inputs. The X9258 compares the  
serial data stream with the address input state; a  
successful compare of all four address bits is required  
Acknowledge  
Acknowledge is a software convention used to provide  
a positive handshake between the master and slave  
devices on the bus to indicate the successful receipt of  
data. The transmitting device, either the master or the  
slave, will release the SDA bus after transmitting eight  
bits. The master generates a ninth clock cycle and  
during this period the receiver pulls the SDA line LOW  
to acknowledge that it successfully received the eight  
bits of data.  
for the X9258 to respond with an acknowledge. The A  
- A inputs can be actively driven by CMOS input  
0
3
signals or tied to V  
or V  
.
CC  
SS  
Acknowledge Polling  
The disabling of the inputs, during the internal  
nonvolatile write operation, can be used to take  
advantage of the typical 5ms nonvolatile write cycle  
time. Once the stop condition is issued to indicate the  
end of the nonvolatile write command the X9258  
initiates the internal write cycle. ACK polling can be  
initiated immediately. This involves issuing the start  
condition followed by the device slave address. If the  
X9258 is still busy with the write operation no ACK will  
be returned. If the X9258 has completed the write  
operation an ACK will be returned and the master can  
then proceed with the next operation.  
The X9258 will respond with an acknowledge after  
recognition of a start condition and its slave address  
and once again after successful receipt of the  
command byte. If the command is followed by a data  
byte the X9258 will respond with a final acknowledge.  
Array Description  
The X9258 is comprised of four resistor arrays. Each  
array contains 255 discrete resistive segments that are  
connected in series. The physical ends of each array  
are equivalent to the fixed terminals of a mechanical  
potentiometer (V /R and V /R inputs).  
H
H
L
L
At both ends of each array and between each resistor  
segment is a CMOS switch connected to the wiper  
(V ) output. Within each individual array only one  
W
switch may be turned on at a time. These switches are  
controlled by the Wiper Counter Register (WCR). The  
8 bits of the WCR are decoded to select, and enable,  
one of 256 switches.  
FN8168.1  
3
May 6, 2005