X5083
Equivalent A.C. Load Circuit at 5V V
A.C. Test Conditions
Input pulse levels
CC
VCC x 0.1 to VCC x 0.9
10ns
5V
5V
Input rise and fall times
Input and output timing level
3.3kΩ
V
CC x 0.5
1.64kΩ
SO
OUTPUT
RESET
1.64kΩ
30pF
100pF
AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)
2.7V-5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
DATA INPUT TIMING
fSCK
tCYC
tLEAD
tLAG
Clock frequency
0
3.3
MHz
ns
Cycle time
300
150
150
130
130
20
CS lead time
ns
CS lag time
ns
tWH
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Input rise time
Input fall time
CS deselect time
ns
tWL
ns
tSU
ns
tH
20
ns
t
RI (Note 3)
2
2
µs
µs
ns
t
FI (Note 3)
tCS
100
0
t
WC (Note 4) Write cycle time
DATA OUTPUT TIMING
fSCK Clock frequency
tDIS
10
ms
3.3
150
130
MHz
ns
Output disable time
Output valid from clock low
Output hold time
tV
ns
tHO
0
ns
t
RO (Note 3)
Output rise time
50
50
ns
t
FO (Note 3)
NOTES:
3. This parameter is periodically sampled and not 100% tested.
Output fall time
ns
4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
FN8127.2
14
September 16, 2005
INTERSIL [ Intersil ]
