X5083
CS
0
1
2
3
4
5
6
7
SCK
Instruction
(1 Byte)
SI
High Impedance
SO
FIGURE 7. WREN/WRDI SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
FIGURE 8. EEPROM ARRAY WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
Data Byte
Instruction
4
6
5
3
2
1
0
SI
W
D
1
B
L
2
B
B
L
0
W
D
0
L
1
High Impedance
SO
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
FN8127.2
10
September 16, 2005