ISL88731C
The STOP condition is a LOW-to-HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be
sent before each START condition.
Undervoltage Detect and Battery Trickle
Charging
If the voltage at CSON falls below 2.5V ISL88731C
reduces the charge current limit to 128mA to trickle
charge the battery. When the voltage rises above 2.7V,
the charge current reverts to the programmed value in
the ChargeCurrent register.
SDA
SCL
Over-Temperature Protection
S
P
If the die temp exceeds +150°C, it stops charging. Once
the die temp drops below +125°C, charging will start up
again.
START
CONDITION
STOP
CONDITION
FIGURE 18. START AND STOP WAVEFORMS
The System Management Bus
Acknowledge
The System Management Bus (SMBus) is a 2-wire bus
that supports bidirectional communications. The protocol
is described briefly here. More detail is available from
www.smbus.org.
Each address and data transmission uses 9-clock pulses.
The ninth pulse is the acknowledge bit (ACK). After the
start condition, the master sends 7-slave address bits
and a R/W bit during the next 8-clock pulses. During the
ninth clock pulse, the device that recognizes its own
address holds the data line low to acknowledge. The
acknowledge bit is also used by both the master and the
slave to acknowledge receipt of register addresses and
data (see Figure 19).
General SMBus Architecture
VDDSMB
SMBUS SLAVE
INPUT
STATE
MACHINE,
REGISTERS,
MEMORY,
ETC
SCL
OUTPUT
INPUT
CONTROL
SMBUS MASTER
INPUT
SCL
SDA
SCL
OUTPUT
INPUT
OUTPUTCONTROL
CONTROL
2
8
1
9
CPU
SDA
SDA
OUTPUT
CONTROL
SMBUS SLAVE
INPUT
OUTPUT
INPUT
MSB
STATE
MACHINE,
REGISTERS,
MEMORY,
ETC
SCL
CONTROL
START
ACKNOWLEDGE
FROM SLAVE
SDA
OUTPUT
CONTROL
2
FIGURE 19. ACKNOWLEDGE ON THE I C BUS
SMBus Transactions
TO OTHER
All transactions start with a control byte sent from the
SMBus master device. The control byte begins with a
Start condition, followed by 7-bits of slave address
(0001001 for the ISL88731C) followed by the R/W bit.
The R/W bit is 0 for a write or 1 for a read. If any slave
devices on the SMBus bus recognize their address, they
will Acknowledge by pulling the serial data (SDA) line low
for the last clock cycle in the control byte. If no slaves
exist at that address or are not ready to communicate,
the data line will be 1, indicating a Not Acknowledge
condition.
SLAVE DEVICES
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can
only change when the clock signal on the SCL line is
LOW. Refer to Figure 17.
SDA
Once the control byte is sent, and the ISL88731C
acknowledges it, the 2nd byte sent by the master must
be a register address byte such as 0x14 for the
ChargeCurrent register. The register address byte tells
the ISL88731C which register the master will write or
read. See Table 1 for details of the registers. Once the
ISL88731C receives a register address byte it responds
with an acknowledge.
SCL
DATA LINE CHANGE
STABLE
OF DATA
DATA VALIDALLOWED
FIGURE 17. DATA VALIDITY
START and STOP Conditions
As shown in Figure 18, START condition is a
HIGH-to-LOW transition of the SDA line while SCL is
HIGH.
FN6978.0
March 8, 2010
12
INTERSIL [ Intersil ]
