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ICL7109CPL 参数 Datasheet PDF下载

ICL7109CPL图片预览
型号: ICL7109CPL
PDF下载: 下载PDF文件 查看货源
内容描述: 12位微处理器兼容A / D转换器 [12-Bit, Microprocessor- Compatible A/D Converter]
分类和应用: 转换器微处理器
文件页数/大小: 25 页 / 947 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
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ICL7109
Design Information Summary Sheet
• OSCILLATOR FREQUENCY
f
OSC
= 0.45/RC
C
OSC
> 50pF; R
OSC
> 50kΩ
f
OSC
(Typ) = 60kHz
or
f
OSC
(Typ) = 3.58MHz Crystal
• OSCILLATOR PERIOD
t
OSC
= RC/0.45
t
OSC
= 1/3.58MHz (Crystal)
• INTEGRATION CLOCK FREQUENCY
f
CLOCK
= f
OSC
(RC Mode)
f
CLOCK
= f
OSC
/58 (Crystal)
t
CLOCK
= 1/f
CLOCK
• INTEGRATION PERIOD
t
INT
= 2048 x t
CLOCK
• 60/50Hz REJECTION CRITERION
t
INT
/t
60Hz
or t
lNT
/t
50Hz
= Integer
• OPTIMUM INTEGRATION CURRENT
I
INT
= 20µA
• FULL-SCALE ANALOG INPUT VOLTAGE
V
lNFS
Typically = 200mV or 2V
• INTEGRATE RESISTOR
V
IN FS
R
I NT
= ----------------
-
I
I NT
• V
INT
MAXIMUM SWING
(V- + 0.5V) < V
INT
< (V+ - 0.5V)
V
INT
(Typ) = 2V
• DISPLAY COUNT
V
IN
-
COUNT
=
2048
×
----------------
V REF
• CONVERSION CYCLE
t
CYC
= t
CL0CK
x 8192
(In Free Run Mode, Run/HOLD = 1)
when f
CLOCK
= 60kHz, t
CYC
= 133ms
• COMMON MODE INPUT VOLTAGE
(V- + 2.0V) < V
lN
< (V+ - 2V)
• AUTO-ZERO CAPACITOR
0.01µF < C
AZ
< 1µF
• REFERENCE CAPACITOR
0.1µF < C
REF
< 1µF
• V
REF
Biased between V+ and V-
V
REF
V+ - 2.8V
Regulation lost when V+ to V-
6.4V.
If V
REF
is not used, float output pin.
• POWER SUPPLY: DUAL
±5.0V
V+ = +5V to GND
V- = -5V to GND
• OUTPUT TYPE
Binary Amplitude with Polarity and Overrange Bits
Tips: Always tie TEST pin HIGH.
Don’t leave any inputs floating.
• INTEGRATE CAPACITOR
(
t
INT
) (
I
IN T
)
C
I NT
= -------------------------------
-
V
INT
• INTEGRATOR OUTPUT VOLTAGE SWING
(
t
INT
) (
I
IN T
)
V
INT
= -------------------------------
-
C
INT
6