HIP6601A, HIP6603A, HIP6604
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
Tes t Circuit
+5V OR +12V
+5V OR +12V
3
2
+12V
--
P = 1.05f
V Q + V Q + I
V
DDQ
0.01µF
sw
U
L
L
CC
U
BOOT
PVCC
where f is the switching frequency of the PWM signal. V
sw
2N7002
U
and V represent the upper and lower gate rail voltage. Q
0.15µF
L
U
UGATE
PHASE
C
U
and Q is the upper and lower gate charge determined by
L
VCC
MOSFET selection and any external capacitance added to
the gate pins. The I product is the quiescent power
V
DDQ CC
LGATE
0.15µF
PWM
of the driver and is typically 30mW.
100kΩ
2N7002
C
L
GND
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
1000
C
= C = 3nF
L
U
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the MOSFET.
800
600
400
200
C
= C = 2nF
L
U
C
= C = 1nF
L
U
C
C
= C = 4nF
L
U
U
VCC = PVCC = 12V
= C = 5nF
L
1
2
1
2
--
--
P
=
f
Q
V
=
f
Q V
SW
REFRESH
SW
LOSS
U
U
PVCC
0
500
1000
1500 2000
FREQUENCY (kHz)
where Q
is the total charge removed from the bootstrap
LOSS
FIGURE 1. POWER DISSIPATION vs FREQUENCY
capacitor and provided to the upper gate load.
The 1.05 factor is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
1000
VCC = PVCC = 12V
C
C
= 3nF
= 0nF
U
L
800
600
400
200
provided. C and C are the upper and lower gate load
U
L
C
= C = 3nF
L
capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value is
0.01µF.
U
C
C
= 0nF
= 3nF
U
L
In Figure 1, C and C values are the same and frequency
U
L
is varied from 50kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply. Curves do exceed the 800mW
cutoff, but continuous operation above this point is not
recommended.
0
500
1000
FREQUENCY (kHz)
1500
2000
Figure 2 shows the dissipation in the driver with 3nF loading
on both gates and each individually. Note the higher upper
gate power dissipation which is due to the bootstrap device
refresh cycle. Again PVCC and VCC are tied together and to
a +12V supply.
FIGURE 2. 3nF LOADING PROFILE
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 4 through 6
show the same characterization for the HIP6603A with a
+5V supply on PVCC and VCC tied to a +12V supply.
7
INTERSIL [ Intersil ]
