HIP6601B, HIP6603B, HIP6604B
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
Tes t Circuit
+5V OR +12V
+5V OR +12V
0.01µF
+12V
3
2
--
P = 1.05f
V Q + V Q + I
VCC
DDQ
BOOT
sw
U
L
L
U
PVCC
2N7002
0.15µF
UGATE
C
where f is the switching frequency of the PWM signal. V
sw
U
U
PHASE
VCC
and V represent the upper and lower gate rail voltage. Q
L
U
and Q is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
L
LGATE
0.15µF
PWM
100kΩ
2N7002
C
the gate pins. The I product is the quiescent power
of the driver and is typically 30mW.
V
L
DDQ CC
GND
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
1000
C
= C = 3nF
L
U
800
600
400
200
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the MOSFET.
C
= C = 2nF
L
U
C
= C = 1nF
L
U
C
C
= C = 4nF
L
= C = 5nF
L
U
U
VCC = PVCC = 12V
0
500
1000
1500
2000
FREQUENCY (kHz)
1
2
1
2
FIGURE 1. POWER DISSIPATION vs FREQUENCY
--
--
P
=
f
Q
V
=
f
Q V
SW
REFRESH
SW
LOSS
U
U
PVCC
1000
VCC = PVCC = 12V
where Q
is the total charge removed from the bootstrap
C
C
= 3nF
= 0nF
LOSS
U
L
capacitor and provided to the upper gate load.
800
600
400
200
The 1.05 factor is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. C and C are the upper and lower gate load
capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value is
0.01µF.
C
= C = 3nF
L
U
C
= 0nF
= 3nF
U
L
U
L
C
In Figure 1, C and C values are the same and frequency
U
L
is varied from 50kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply. Curves do exceed the 800mW
cutoff, but continuous operation above this point is not
recommended.
0
500
1000
FREQUENCY (kHz)
1500
2000
FIGURE 2. 3nF LOADING PROFILE
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate capacitors
are varied from 1nF to 5nF. VCC and PVCC are tied together
and to a +12V supply. Figures 4, 5 and 6 show the same
characterization for the HIP6603B with a +5V supply on PVCC
and VCC tied to a +12V supply.
Figure 2 shows the dissipation in the driver with 3nF loading
on both gates and each individually. Note the higher upper
gate power dissipation which is due to the bootstrap device
refresh cycle. Again PVCC and VCC are tied together and to
a +12V supply.
Since both upper and lower gate capacitance can vary,
Figure 8 shows dissipation curves versus lower gate
capacitance with upper gate capacitance held constant at three
different values. These curves apply only to the HIP6601B due
to power supply configuration.
FN9072.7
7
July 20, 2005
INTERSIL [ Intersil ]
