HIP6601B, HIP6603B, HIP6604B
Lower gate driver supply voltage.
Functional Pin Des cription
PVCC (Pin 7), (Pin 11 QFN)
UGATE (Pin 1), (Pin 16 QFN)
For the HIP6601B and the HIP6604B, this pin supplies the
upper gate drive bias. Connect this pin from +12V down to +5V.
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
For the HIP6603B, this pin supplies both the upper and
lower gate drive bias. Connect this pin to either +12V or +5V.
BOOT (Pin 2), (Pin 2 QFN)
Floating bootstrap supply pin for the upper gate drive.
Connect a bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. A resistor in series with boot
capacitor is required in certain applications to reduce ringing
on the BOOT pin. See the Internal Bootstrap Device section
under DESCRIPTION for guidance in choosing the
appropriate capacitor and resistor values.
PHASE (Pin 8), (Pin 14 QFN)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. The PHASE voltage is
monitored for adaptive shoot-through protection. This pin
also provides a return path for the upper gate drive.
Des cription
PWM (Pin 3), (Pin 3 QFN)
Operation
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
Designed for versatility and speed, the HIP6601B, HIP6603B
and HIP6604B dual MOSFET drivers control both high-side
and low-side N-Channel FETs from one externally provided
PWM signal.
GND (Pin 4), (Pin 4 QFN)
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Bias and reference ground. All signals are referenced to
this node.
PGND (Pin 5 QFN Package Only)
This pin is the power ground return for the lower gate driver.
Diagram). After a short propagation delay [t
], the
PDLLGATE
lower gate begins to fall. Typical fall times [t
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
] are
FLGATE
LGATE (Pin 5), (Pin 7 QFN)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
determines the upper gate delay time [t
] based
PDHUGATE
on how quickly the LGATE voltage drops below 2.2V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
VCC (Pin 6), (Pin 9 QFN)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND.
LVCC (Pin 10 QFN Package Only)
[t
] and the upper MOSFET turns on.
RUGATE
Timing Diagram
PWM
t
PDHUGATE
t
PDLUGATE
t
RUGATE
t
FUGATE
UGATE
LGATE
t
RLGATE
t
FLGATE
t
t
PDHLGATE
PDLLGATE
FN9072.7
5
July 20, 2005
INTERSIL [ Intersil ]
