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DG411DYZ 参数 Datasheet PDF下载

DG411DYZ图片预览
型号: DG411DYZ
PDF下载: 下载PDF文件 查看货源
内容描述: 单片四路SPST , CMOS模拟开关 [Monolithic Quad SPST, CMOS Analog Switches]
分类和应用: 开关
文件页数/大小: 13 页 / 354 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
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DG411, DG412, DG413
Electrical Specifications
(Single Supply) Test Conditions: V+ = +12V, V- = 0V, V
L
= 5V, V
IN
= 2.4V, 0.8V (Note 3),
Unless Otherwise Specified.
(Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 4)
TYP
(Note 5)
MAX
(Note 4)
UNITS
PARAMETER
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 13.2V, V- = 0V
V
IN
= 0V or 5V
25
85
25
85
-
-
-1
-5
-
-
-1
-5
0.0001
-
-0.0001
-
0.0001
-
-0.0001
-
1
5
-
-
1
5
-
-
μA
μA
μA
μA
μA
μA
μA
μA
Negative Supply Current, I-
Logic Supply Current, I
L
25
85
Ground Current, I
GND
25
85
NOTES:
3. V
IN
= input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
V
O
is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
3V
LOGIC
INPUT
50%
0V
t
OFF
SWITCH
INPUT V
S
V
O
SWITCH
OUTPUT
0V
t
ON
90%
90%
t
r
< 20ns
t
f
< 20ns
SWITCH
INPUT
S
1
IN
1
LOGIC
INPUT
GND
R
L
V-
-15V
C
L
+5V
V
L
V+
D
1
+15V
SWITCH
OUTPUT
V
O
NOTE: Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENTS POINTS
Repeat test for all IN and S.
For load conditions, see Specifications. C
L
includes fixture and stray
R
L
capacitance.
-
V
O
=
V
S
-----------------------------------
R
L
+
r
DS
(
ON
)
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
3V
LOGIC
INPUT
V
L
0V
V
S1
90%
V
S2
= 10V
0V
V
S2
90%
SWITCH
OUTPUT
V
O2
0V
t
D
t
D
IN
1
, IN
2
LOGIC
INPUT
S
1
V
S1
= 10V
S
2
+5V
V+
+15V
D
1
D
2
R
L2
300Ω
V
O2
R
L1
300Ω
V
O1
C
L1
35pF
SWITCH
OUTPUT
(V01)
C
L2
35pF
GND
V-
-15V
C
L
includes fixture and
stray capacitance.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. BREAK-BEFORE-MAKE TIME
FIGURE 2B. TEST CIRCUITS
6
FN3282.13
June 20, 2007