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DG411DYZ 参数 Datasheet PDF下载

DG411DYZ图片预览
型号: DG411DYZ
PDF下载: 下载PDF文件 查看货源
内容描述: 单片四路SPST , CMOS模拟开关 [Monolithic Quad SPST, CMOS Analog Switches]
分类和应用: 开关
文件页数/大小: 13 页 / 354 K
品牌: INTERSIL [ Intersil ]
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DG411, DG412, DG413  
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, V = 5V, V = 2.4V, 0.8V (Note 3),  
L
IN  
Unless Otherwise Specified. (Continued)  
TEMP  
(°C)  
MIN  
(Note 4)  
TYP  
(Note 5)  
MAX  
(Note 4)  
PARAMETER  
POWER SUPPLY CHARACTERISTICS  
TEST CONDITIONS  
UNITS  
Positive Supply Current, I+  
V+ = 13.2V, V- = 0V  
= 0V or 5V  
25  
85  
25  
85  
25  
85  
25  
85  
-
-
0.0001  
1
5
-
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
V
IN  
-
Negative Supply Current, I-  
-1  
-5  
-
-0.0001  
-
-
Logic Supply Current, I  
0.0001  
1
5
-
L
-
-
Ground Current, I  
-1  
-5  
-0.0001  
-
GND  
-
NOTES:  
3. V = input voltage to perform proper function.  
IN  
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.  
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.  
Test Circuits and Waveforms  
V
is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing  
O
edge of the output waveform.  
+5V  
+15V  
3V  
t < 20ns  
r
t < 20ns  
f
V
V+  
L
SWITCH  
OUTPUT  
LOGIC  
INPUT  
50%  
D
1
SWITCH  
INPUT  
0V  
S
V
1
1
O
t
OFF  
IN  
SWITCH  
INPUT  
V
S
C
R
L
L
LOGIC  
INPUT  
V
O
V-  
-15V  
90%  
90%  
GND  
SWITCH  
OUTPUT  
0V  
Repeat test for all IN and S.  
For load conditions, see Specifications. C includes fixture and stray  
t
ON  
L
R
capacitance.  
L
NOTE: Logic input waveform is inverted for switches that have the  
opposite logic sense.  
------------------------------------  
L
V
= V  
S
O
R
+ r  
DS(ON)  
FIGURE 1A. MEASUREMENTS POINTS  
FIGURE 1B. TEST CIRCUIT  
FIGURE 1. SWITCHING TIMES  
3V  
0V  
+5V  
+15V  
V
V+  
L
LOGIC  
INPUT  
V
S
S
D
O1  
1
2
1
2
V
V
= 10V  
= 10V  
S1  
S2  
V
S1  
C
R
L1  
35pF  
SWITCH  
OUTPUT  
(V01)  
L1  
300Ω  
V
90%  
O2  
D
R
0V  
C
L2  
L2  
35pF  
IN , IN  
1
2
V
S2  
300Ω  
90%  
LOGIC  
INPUT  
SWITCH  
OUTPUT  
V-  
GND  
C
includes fixture and  
0V  
L
V
O2  
-15V  
stray capacitance.  
t
t
D
D
FIGURE 2A. MEASUREMENT POINTS  
FIGURE 2. BREAK-BEFORE-MAKE TIME  
FIGURE 2B. TEST CIRCUITS  
FN3282.13  
June 20, 2007  
6
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