CD4514BMS, CD4515BMS
Logic Diagram
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
VDD
S0
S1
11
9
10
8
S2
S3
VSS
7
S4
S5
S6
S7
*
A
DATA 1
DATA 2
2
3
S
R
Q
Q
6
5
4
*
B
S
R
Q
Q
18 S8
*
DATA 3 21
C
D
S
R
Q
Q
S9
17
S10
S11
S12
20
19
14
*
DATA 4 22
S
R
Q
Q
*
STROBE
1
13 S13
16
*
A B C D
A B C D
INHIBIT 23
S14
15 S15
THESE INVENTERS USED ONLY ON CD4515BMS
* All inputs protected by CMOS protection network.
FIGURE 1. LOGIC DIAGRAM
TRUTH TABLE
DECODER INPUTS
SELECTED OUTPUT
CD4514BMS = LOGIC 1 (HIGH)
CD4515BMS = LOGIC 0 (LOW)
INHIBIT
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
All Outputs = 0, CD4514BMS
All Outputs = 1, CD4515BMS
1 = HIGH LEVEL
0 = LOW LEVEL
X = DON’T CARE
7-1193
INTERSIL [ Intersil ]
