CD4070BMS, CD4077BMS
Schematics
VDD
p
VDD
p
B*
2 (5, 9, 12)
n
n
TRUTH TABLE CD4070BMS
1 OF 4 GATES
p
VSS
VDD
A
0
1
0
1
B
0
0
1
1
J
0
1
1
0
p
p
J
3 (4, 10, 11)
n
p
n
n
A*
1 (6, 8, 13)
1 = High Level
0 = Low Level
J = A B
VDD
VSS
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
*
VSS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070BMS (1 OF 4 IDENTICAL GATES)
VDD
p
VDD
p
B*
2 (5, 9, 12)
n
n
n
TRUTH TABLE CD4077BMS
1 OF 4 GATES
p
VSS
VDD
A
0
1
0
1
B
0
0
1
1
J
1
0
0
1
p
J
3 (4, 10, 11)
n
p
n
n
A*
1 (6, 8, 13)
1 = High Level
0 = Low Level
VDD
J = A
B
VSS
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
*
VSS
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077BMS (1 OF 4 IDENTICAL GATES)
7-460
INTERSIL [ Intersil ]
