ADC0803, ADC0804
Timing Waveforms
V+
(Continued)
t
r
= 20ns
V+
RD
0.8V
DATA
OUTPUT
C
L
DATA
OUTPUTS
V+
V
OI
t
r
2.4V
90%
50%
10%
t
0H
10K
RD
CS
10%
FIGURE 1C. t
0H
FIGURE 1D. t
0H
, C
L
= 10pF
FIGURE 1. THREE-STATE CIRCUITS AND WAVEFORMS
Typical Performance Curves
LOGIC INPUT THRESHOLD VOLTAGE (V)
1.8
-55
o
C TO 125
o
C
500
1.7
400
DELAY (ns)
4.75
5.00
5.25
5.50
1.6
300
1.5
200
1.4
1.3
4.50
100
0
200
400
600
LOAD CAPACITANCE (pF)
800
1000
V+ SUPPLY VOLTAGE (V)
FIGURE 2. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY
VOLTAGE
FIGURE 3. DELAY FROM FALLING EDGE OF RD TO OUTPUT
DATA VALID vs LOAD CAPACITANCE
3.5
CLK IN THRESHOLD VOLTAGE (V)
1000
R = 10K
3.1
V
T(+)
R = 50K
f
CLK
(kHz)
V
T(-)
100
10
2.7
-55
o
C TO 125
o
C
2.3
1.9
R = 20K
1.5
4.50
4.75
5.00
5.25
5.50
V+ SUPPLY VOLTAGE (V)
100
CLOCK CAPACITOR (pF)
1000
FIGURE 4. CLK IN SCHMITT TRIP LEVELS vs SUPPLY
VOLTAGE
FIGURE 5. f
CLK
vs CLOCK CAPACITOR
5
INTERSIL [ INTERSIL CORPORATION ]
