ADC0803, ADC0804
successive approximation register. A correction is made to
input at 5V, this DC current is at a maximum of approximately
1
offset the comparison by / LSB (see Figure 11A).
2
5µA. Therefore, bypass capacitors should not be used at
the analog inputs or the V
/2 pin for high resistance
REF
Analog Differential Voltage Inputs and Common-
Mode Rejection
sources (>1kΩ). If input bypass capacitors are necessary for
noise filtering and high source resistance is desirable to
minimize capacitor size, the effects of the voltage drop across
this input resistance, due to the average value of the input
current, can be compensated by a full scale adjustment while
the given source resistor and input bypass capacitor are both
in place. This is possible because the average value of the
input current is a precise linear function of the differential input
voltage at a constant conversion rate.
This A/D gains considerable applications flexibility from the
analog differential voltage input. The V
input (pin 7) can
lN(-)
be used to automatically subtract a fixed voltage value from
the input reading (tare correction). This is also useful in 4mA
- 20mA current loop conversion. In addition, common-mode
noise can be reduced by use of the differential input.
1
The time interval between sampling V
and V
lN(-)
is 4 /
IN(+)
2
clock periods. The maximum error voltage due to this slight
time difference between the input voltage samples is given by:
Input Source Resistance
Large values of source resistance where an input bypass
capacitor is not used will not cause errors since the input
currents settle out prior to the comparison time. If a low-
pass filter is required in the system, use a low-value series
resistor (≤1kΩ) for a passive RC section or add an op amp
RC active low-pass filter. For low-source-resistance
applications (≤1kΩ), a 0.1µF bypass capacitor at the inputs
will minimize EMI due to the series lead inductance of a long
wire. A 100Ω series resistor can be used to isolate this
capacitor (both the R and C are placed outside the feedback
loop) from the output of an op amp, if used.
4.5
CLK
∆V (MAX) = (V
)(2πf
) ------------
E
PEAK
CM
f
where:
∆V is the error voltage due to sampling delay,
E
V
f
is the peak value of the common-mode voltage,
PEAK
is the common-mode frequency.
CM
For example, with a 60Hz common-mode frequency, f , and
CM
1
a 640kHz A/D clock, f
, keeping this error to / LSB (~5mV)
CLK
4
would allow a common-mode voltage, V
, given by:
PEAK
Stray Pickup
∆V
E(MAX)(f
)
CLK
The leads to the analog inputs (pins 6 and 7) should be kept
as short as possible to minimize stray signal pickup (EMI).
Both EMI and undesired digital-clock coupling to these inputs
can cause system errors. The source resistance for these
inputs should, in general, be kept below 5kΩ. Larger values of
source resistance can cause undesired signal pickup. Input
bypass capacitors, placed from the analog inputs to ground,
will eliminate this pickup but can create analog scale errors as
these capacitors will average the transient input switching
currents of the A/D (see Analog Input Current). This scale
error depends on both a large source resistance and the use
of an input bypass capacitor. This error can be compensated
by a full scale adjustment of the A/D (see Full Scale
V
= -------------------------------------------------- ,
PEAK
(2πf
)(4.5)
CM
or
–3
3
(5 × 10 )(640 × 10 )
= --------------------------------------------------------- 1.9V .
(6.28)(60)(4.5)
V
PEAK
The allowed range of analog input voltage usually places
more severe restrictions on input common-mode voltage
levels than this.
An analog input voltage with a reduced span and a relatively
large zero offset can be easily handled by making use of the
differential input (see Reference Voltage Span Adjust).
Analog Input Current
Adjustment) with the source resistance and input bypass
capacitor in place, and the desired conversion rate.
The internal switching action causes displacement currents to
flow at the analog inputs. The voltage on the on-chip
capacitance to ground is switched through the analog
differential input voltage, resulting in proportional currents
Reference Voltage Span Adjust
For maximum application flexibility, these A/Ds have been
designed to accommodate a 5V, 2.5V or an adjusted voltage
reference. This has been achieved in the design of the IC as
shown in Figure 12.
entering the V
IN(+)
input and leaving the V input. These
IN(-)
current transients occur at the leading edge of the internal
clocks. They rapidly decay and do not inherently cause errors
as the on-chip comparator is strobed at the end of the clock
perIod.
1
Notice that the reference voltage for the IC is either / of the
2
voltage which is applied to the V+ supply pin, or is equal to
Input Bypass Capacitors
the voltage which is externally forced at the V
/2 pin. This
REF
Bypass capacitors at the inputs will average these charges
and cause a DC current to flow through the output resistances
of the analog signal sources. This charge pumping action is
allows for a pseudo-ratiometric voltage reference using, for
the V+ supply, a 5V reference voltage. Alternatively, a
voltage less than 2.5V can be applied to the V
/2 input.
REF
worse for continuous conversions with the V
at full scale. For a 640kHz clock frequency with the V
input voltage
IN(+)
The internal gain to the V
/2 input is 2 to allow this factor
REF
IN(+)
of 2 reduction in the reference voltage.
9
INTERSIL [ Intersil ]
