ADC0803, ADC0804
Electrical Specifications
PARAMETER
CONTROL INPUTS
(Note 7)
Logic “1“ Input Voltage (Except Pin 4 CLK
IN), V
INH
Logic “0“ Input Voltage (Except Pin 4 CLK
IN), V
INL
CLK IN (Pin 4) Positive Going Threshold
Voltage, V+
CLK
CLK IN (Pin 4) Negative Going Threshold
Voltage, V-
CLK
CLK IN (Pin 4) Hysteresis, V
H
Logic “1” Input Current (All Inputs), I
INHI
Logic “0” Input Current (All Inputs), I
INLO
DATA OUTPUTS AND INTR
Logic “0” Output Voltage, V
OL
Logic “1” Output Voltage, V
OH
Three-State Disabled Output Leakage (All
Data Buffers)
, I
LO
Output Short Circuit Current, I
SOURCE
Output Short Circuit Current, I
SINK
NOTES:
2. All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to the DGND,
being careful to avoid ground loops.
3. For V
IN(-)
≥
V
IN(+)
the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will
forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be careful, during testing
at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct - especially at elevated temperatures, and cause
errors for analog inputs near full scale. As long as the analog V
IN
does not exceed the supply voltage by more than 50mV, the output code will
be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over temperature
variations, initial tolerance and loading.
4. With V+ = 6V, the digital logic interfaces are no longer TTL compatible.
5. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process.
6. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide pulse width will
hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams).
7. CLK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
8. None of these A/Ds requires a zero-adjust. However, if an all zero code is desired for an analog input other than 0V, or if a narrow full scale span exists
(for example: 0.5V to 4V full scale) the V
IN(-)
input can be adjusted to achieve this. See the Zero Error description in this data sheet.
l
O
= 1.6mA, V+ = 4.75V
l
O
= -360µA, V+ = 4.75V
V
OUT
= 0V
V
OUT
= 5V
V
OUT
Short to GND, T
A
= 25
o
C
V
OUT
Short to V+, T
A
= 25
o
C
-
2.4
-3
-
4.5
9.0
-
-
-
-
6
16
0.4
-
-
3
-
-
V
V
µA
µA
mA
mA
V
lN
= 5V
V
lN
= 0V
V+ = 5.25V
V+ = 4.75V
2.0
-
2.7
1.5
0.6
-
-1
-
-
-
3.1
1.8
1.3
0.005
-0.005
1.3
V+
0.8
3.5
2.1
2.0
1
-
2.5
V
V
V
V
V
µΑ
µA
mA
(Notes 2, 8)
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC DIGITAL LEVELS AND DC SPECIFICATIONS
V+ = 5V, and T
MIN
to T
MAX
, Unless Otherwise Specified
Supply Current (Includes Ladder Current), I+ f
CLK
= 640kHz, T
A
= 25
o
C and CS = Hl
Timing Waveforms
2.4V
RD
RD
CS
C
L
DATA
OUTPUT
10K
DATA
OUTPUTS
0.8V
V
OH
GND
t
r
= 20ns
t
r
90%
50%
10%
t
1H
90%
V+
FIGURE 1A. t
1H
FIGURE 1B. t
1H
, C
L
= 10pF
4
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