HS-565BRH, HS-565BEH
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in gain and
offset of the D/A converter resulting from a change in -15V or
+15V supplies. It is specified under DC conditions and expressed
as parts per million of full scale range per percent of change in
power supply (ppm of FSR/%).
No Trim Operation
The HS-565BRH, HS-565BEH will perform as specified without
calibration adjustments. To operate without calibration,
substitute 50Ω resistors for the 100Ω trimming
potentiometers: In Figure 2 replace R2 with 50Ω; also remove
the network on pin 8 and connect 50Ω to ground. For bipolar
operation in Figure 3, replace R3 and R4 with 50Ω resistors.
Typical unipolar zero will be ±0.50 LSB plus the op amp offset.
The feedback capacitor C must be selected to minimize settling
time.
R4
100Ω
REF OUT
VCC
4
3
Compliance
Compliance Voltage is the maximum output voltage range that
can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and makes
no claims to accuracy.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times. Worst
case glitches usually occur at half scale or the major carry code
transition from 011 . . . 1 to 100 . . . 0 or vice versa. For example,
if turn ON is greater than turn OFF for 011 . . . 1 to 100 . . . 0, an
intermediate state of 000 . . . 0 exists, such that, the output
momentarily glitches toward zero output. Matched switching
times and fast switching will reduce glitches considerably.
R3
100Ω
BIP.
OFF.
8
11
20V SPAN
HS-565BRH
+
-
10V
IREF
0.5mA
+
-
9.95k
DAC
IO
(4 x IREF
x CODE)
2.5k
5k
5k
10
10V SPAN
C
VO
6 19.95k
REF
IN
5
REF
GND
3.5k
3k
DAC
OUT
9
-
Applying the HS-565BRH and
HS-565BEH
OP AMP Selection
The HS-565BRH, HS-565BEH current output may be converted to
voltage using the standard connections shown in Figures 2 and 3.
The choice of operational amplifier should be reviewed for each
application, since a significant trade-off may be made between
speed and accuracy. Remember settling time for the
DAC-amplifier combination is:
D
A
where t
D
, t
A
are settling times for the DAC and amplifier.
100kΩ
R2
100Ω
REF OUT
VCC
4
3
HS-565BRH
+
-
10V
IREF
0.5mA
+
-
9.95k
DAC
IO
(4 x IREF
x CODE)
2.5k
5k
5k
10
BIP.
OFF.
8
11
20V SPAN
100Ω
+15V
R1
50kΩ
-15V
+
R (SEE
TABLE 1)
CODE
INPUT
7
-VEE
PWR
GND
24 . . . . . 13
MSB
LSB
FIGURE 3. BIPOLAR VOLTAGE OUTPUT
Calibration
Calibration provides the maximum accuracy from a converter by
adjusting its gain and offset errors to zero. For the HS-565BRH,
HS-565BEH, these adjustments are similar whether the current
output is used, or whether an external op amp is added to
convert this current to a voltage. Refer to Table 1 for the voltage
output case, along with Figure 2 or 3.
Calibration is a two step process for each of the five output
ranges shown in Table 1. First adjust the negative full scale (zero
for unipolar ranges). This is an offset adjust which translates the
output characteristic, i.e., affects each code by the same
amount.
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
For the bipolar ranges, this approach leaves an error at the zero
code, whose maximum values is the same as for integral
nonlinearity error. In general, only two values of output may be
calibrated exactly; all others must tolerate some error. Choosing
the extreme end points (plus and minus full scale) minimizes this
distributed error for all other codes.
(
t
)
2
+
(
t
)
2
10V SPAN
C
VO
6
REF
IN
5
REF
GND
19.95k
3.5k
3k
DAC
OUT
9
-
+
R (SEE
TABLE 1)
CODE
INPUT
7
-VEE
PWR
GND
24 . . . . . 13
MSB
LSB
FIGURE 2. UNIPOLAR VOLTAGE OUTPUT
4
FN4607.4
May 7, 2012
INTERSIL [ INTERSIL CORPORATION ]
