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5962R9675501VJC 参数 Datasheet PDF下载

5962R9675501VJC图片预览
型号: 5962R9675501VJC
PDF下载: 下载PDF文件 查看货源
内容描述: 抗辐射高速,单片式数位类比转换器 [Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter]
分类和应用: 转换器
文件页数/大小: 7 页 / 128 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
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HS-565ARH
TABLE 1. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
MODE
Bipolar (See Figure 2)
OUTPUT
RANGE
±10V
±5V
±2.5V
PIN 10
TO
NC
VO
VO
PIN 11
TO
VO
Pin 10
Pin 9
RESISTOR
(R)
1.69K
1.43K
1.1K
APPLY
INPUT CODE
All 0’s
All 1’s
All 0’s
All 1’s
All 0’s
All 1’s
CALIBRATION
ADJUST
R3
R4
R3
R4
R3
R4
TO SET VO
-10V
+9.99512V
-5V
+4.99756V
-2.5V
+2.49878V
OUT
SYNC
PULSE
PULSE
IN
GENERATOR
GENERATOR
TRIG
NO. 1
NO. 2
OUT
20V
±
20%
BIAS
HS-565ARH
OUT
C
A
24
23
.
.
.
.
.
.
.
.
.
.
.
.
.
14
13
8
11
5K
9.95K
10
TURN ON
TURN OFF
+3V
NC
A
50%
0V
-0.50LSB
0V
DIGITAL
INPUT
DAC
OUTPUT
SETTLING TIME
tD = COMPARATOR DELAY
5K
9
B
+
-
2.5K
2mA
12
5
STROBE IN
D
COMPARATOR
OUT
B
~100
kHz
P
5V
-400mV
(TURN OFF)
tX
2V
90
200K
0.1µF
VLSB
SUPPLY
D
C
LSB
50%
0.8V
4V
0V
COMP.
STROBE
“EQUAL BRIGHTNESS”
COMP.
OUT
DVM
10
FIGURE 3A. .
FIGURE 3B.
Other Considerations
Grounds
The HS-565ARH has two ground terminals, pin 5 (REF GND)
and pin 12 (PWR GND). These should not be tied together
near the package unless that point is also the system signal
ground to which all returns are connected. (If such a point
exists, then separate paths are required to pins 5 and 12).
The current through pin 5 is near zero DC (Note); but pin 12
carries up to 1.75mA of code - dependent current from bits
1, 2, and 3. The general rule is to connect pin 5 directly to
the system “quiet” point, usually called signal or analog
ground. Connect pin 12 to the local digital or power ground.
Then, of course, a single path must connect the
analog/signal and digital/power grounds.
NOTE: Current cancellation is a two step process within the HS-
565ARH in which code dependent variations are eliminated, the
resulting DC current is supplied internally. First an auxiliary 9-bit R-
2R ladder is driven by the complement of the DACs input code.
Together, the main and auxiliary ladders draw a continuous 2.25mA
from the internal ground node, regardless of input code. Part of the
DC current is supplied by the zener voltage reference, and the
remainder is sourced from the positive supply via a current mirror
which is laser trimmed for zero current through the external terminal
(pin 5).
Layout
Connections to pin 9 (IOUT) on the HS-565ARH are most
critical for high speed performance. Output capacitance of the
DAC is only 20pF, so a small change of additional capacitance
may alter the op amp’s stability and affect settling time.
Connections to pin 9 should be short and few. Component
leads should be short on the side connecting to pin 9 (as for
feedback capacitor C). See the Settling Time section.
Bypass Capacitors
Power supply bypass capacitors on the op amp will serve the
HS-565ARH also. If no op amp is used, a 0.01µF ceramic
capacitor from each supply terminal to pin 12 is sufficient,
since supply current variations are small.
6