HS-565ARH
Calibration
Calibration provides the maximum accuracy from a
converter by adjusting its gain and offset errors to zero, For
the HS-565ARH, these adjustments are similar whether the
current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 7
for the voltage output case, along with Figure 1 or 2.
Calibration is a two step process for each of the five output
ranges shown in Table 7. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e. affects each code by
the same amount.
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum values is the same as for
integral nonlinearity error. In general, only two values of
output may be calibrated exactly; all others must tolerate
some error. Choosing the extreme end points (plus and
minus full scale) minimizes this distributed error for all other
codes.
The usual specification is based on a 10V step, produced by
simultaneously switching all bits from off-to-on (tON) or on-
to-off (tOFF). The slower of the two cases is specified, as
measured from 50% of the digital input transition to the final
entry within a window of 0.50 LSB about the settled v
alue.
Four measurements characterize a given type of DAC:
(a) tON, to final value +0.50 LSB
(b) tON, to final value -0.50 LSB
(c) tOFF, to final value +0.50 LSB
(d) OFF, to final value -0.50 LSB
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.50 LSB). For example, refer to Figures 3A and 3B
for the measurement of case (d).
Procedure
As shown in Figure 3B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX,
• Adjust the delay on generator number 2 for a tX of
several microseconds. This assures that the DAC
output has settled to its final wave.
• Switch on the LSB (+5V)
• Adjust the VLSB supply for 50% triggering at
COMPARATOR OUT. This is indicated by traces of
equal brightness on the oscilloscope display as shown
in Figure 3B. Note DVM reading.
• Switch to LSB to Pulse (P)
• Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the
difference in the DVM readings noted above.
• Adjust the VLSB supply to reduce the DVM reading by
5 LSBs (DVM reads 10X, so this sets the comparator to
sense the final settled value minus 0.50 LSB).
Comparator output disappears.
• Reduce generator number 2 delay until comparator
output reappears, and adjust for “equal brightness”.
• Measure tX from scope as shown in Figure 3B. Settling
time equals tX + tD, i.e. tX + 15ns.
Settling Time
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test methods before using the specified
settling time as a basis for design.
The approach used for several years at Intersil calls for a
strobed comparator to sense final perturbations of the DAC
output waveform. This gives the LSB a reasonable
magnitude (814mV for the HS-565ARH, which provides the
comparator with enough overdrive to establish an accurate
±0.50
LSB window about the final settled value. Also, the
required test conditions simulate the DACs environment for a
common application - use in a successive approximation
A/D converter. Considerable experience has shown this to
be a reliable and repeatable way to measure settling time.
TABLE 1. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
MODE
Unipolar (See Figure 1)
OUTPUT
RANGE
0 to +10V
0 to +5V
PIN 10
TO
VO
VO
PIN 11
TO
Pin 10
Pin 9
RESISTOR
(R)
1.43K
1.1K
APPLY
INPUT CODE
All 0’s
All 1’s
All 0’s
All 1’s
CALIBRATION
ADJUST
R1
R2
R1
R2
TO SET VO
0V
+9.99756V
0V
+4.99878V
5
INTERSIL [ INTERSIL CORPORATION ]
