Specifications HS-80C85RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Input Capacitance
I/O Capacitance
Output Capacitance
NOTE:
1. All measurements referenced to device ground.
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
NOTE:
The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2.
TABLE 5. BURN-IN DELTA PARAMETERS (+25
o
C; In Accordance With SMD)
SYMBOL
CIN
CI/O
COUT
(NOTE 1)
CONDITIONS
VDD = Open, f = 1MHz
VDD = Open, f = 1MHz
VDD = Open, f = 1MHz
TEMPERATURE
T
A
= +25
o
C
T
A
= +25
o
C
T
A
= +25
o
C
MIN
-
-
-
MAX
12
13
12
UNITS
pF
pF
pF
TABLE 6. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY
ADDRESS BRANCHED TO (1)
WHEN INTERRUPT OCCURS
24H
3CH
34CH
2CH
See Note 2
NAME
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
NOTES:
PRIORITY
1
2
3
4
5
TYPE TRIGGER
Rising edge and high level until sampled.
Rising edge (latched)
High level until sampled.
High level until sampled.
High level until sampled.
1. The processor pushes the PC on the stack before branching to the indicated address.
2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.
TABLE 7. BUS TIMING SPECIFICATION AS A t
CYC
DEPENDENT
SYMBOL
tAL
tLA
tLL
tLCK
tLC
tAD
tRD
tRAE
tCA
tDW
tWD
HS-8OC85RH
(1/2)T- 175
(1/2)T- 175
(1/2)T-50
(1/2)T- 125
(1/2)T- 100
(5/2 + N)T - 375
(3/2 + N)T - 375
(1/2)T- 130
(1/2)T - 100
(3/2 + N)T - 175
(1/2)T-100
Minimum
Minimum
Minimum
Minimum
Minimum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
SYMBOL
tCC
tCL
tARY
tHACK
tHABF
tHABE
tAC
t1
t2
tRV
tLDR
HS-8OC85RH
(3/2 + N)T - 175
(1/2)T - 190
(3/2)T - 500
(1/2)T - 160
(1/2)T +125
(1/2)T +125
(2/2)T - 200
(1/2)T-210
(1/2)T- 150
(3/2)T - 200
(4/2)T - 325
Minimum
Minimum
Maximum
Minimum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
Maximum
NOTE: N is equal to the total WAIT states T = tCYC
Spec Number
7
518054
INTERSIL [ INTERSIL CORPORATION ]
