Specifications HS-80C85RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
GROUP A
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
LIMITS
TEMPERATURE
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
-55
o
C, +25
o
C, +125
o
C
MIN
75
125
250
150
575
60
575
-
-
90
-
-
-
-
75
150
125
675
-
200
-
120
375
550
-
-
250
150
-
MAX
-
-
-
-
-
-
-
375
375
-
0
300
0
375
-
-
-
-
350
-
175
-
-
-
0
0
-
-
50
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
A8-15 Valid Before Trailing Edge of ALE (Note 5)
A0-7 Valid Before Trailing Edge of ALE
READY Valid from Address
Valid
Address (A8-15) Valid After Control
Width of Control Low (RD, WR, INTA) Edge of
ALE
Trailing Edge of Control to Leading Edge of ALE
Data Valid to Trailing Edge of WRITE
HLDA to Bus Enable
Bus Float After HLDA
HLDA Valid to Trailing Edge of CLK
HOLD Hold Time
HOLD Setup Time to Trailing Edge of CLK
INTR Hold Time
INTR, RST and TRAP Setup Time to Falling
Edge of CLK
Address Hold Time After ALE
Trailing Edge of ALE to Leading Edge of Control
ALE Low During CLK High
ALE to Valid Data During Read
ALE to Valid Data During Write
ALE Width
ALE to READY Stable
Trailing Edge of READ to Re-Enabling the Ad-
dress
READ (or INTA) to Valid Data
Control Trailing Edge to Leading Edge of Next
Control
Data Hold Time After READ INTA
READY Hold Time
READY Setup Time to Leading Edge of CLK
Data Valid After Trailing Edge of WRITE
LEADING Edge of WRITE to Data Valid
NOTES:
SYMBOL
TAL
tALL
TARY
TCA
TCC
TCL
TDW
THABE
THABF
THACK
THDH
THDS
TINH
TINS
TLA
TLC
TLCK
TLDR
TLDW
TLL
TLRY
TRAE
TRD
TRV
TRDH
TRYH
TRYS
TWD
TWDL
1. Output timings are measured with a purely capacitive load, CL = 150pF
2. VDD = 4.75V, VIH = 4.25V, VIL = 0.8V
3. Delay times are measured with a 1MHz clock. An algorithm is used to convert the delays into the AC timings above with a TCYC = 500ns.
4. The AC table is tested as shown above to guarantee the processor system timing.
5. A8 - A15 address specifications also apply to IO/M, S0 and S1 except A8 - A15 are undefined during T4-T6 of off cycle whereas IO/M,
So, and S1 are stable.
Spec Number
6
518054
INTERSIL [ INTERSIL CORPORATION ]
