Specifications HS-80C85RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
GROUP A
PARAMETER
SYMBOL SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
ns
o
o
o
A8-15 Valid Before Trailing Edge of ALE (Note 5)
A0-7 Valid Before Trailing Edge of ALE
TAL
tALL
9, 10, 11
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
75
-
-
-
o
o
o
-55 C, +25 C, +125 C
125
250
ns
o
o
o
READY Valid from Address
Valid
TARY
-55 C, +25 C, +125 C
ns
o
o
o
Address (A8-15) Valid After Control
TCA
TCC
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
150
575
-
-
ns
ns
o
o
o
Width of Control Low (RD, WR, INTA) Edge of
ALE
-55 C, +25 C, +125 C
o
o
o
Trailing Edge of Control to Leading Edge of ALE
Data Valid to Trailing Edge of WRITE
HLDA to Bus Enable
TCL
TDW
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
60
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
o
o
o
-55 C, +25 C, +125 C
575
o
o
o
THABE
THABF
THACK
THDH
THDS
TINH
-55 C, +25 C, +125 C
-
-
375
375
-
o
o
o
Bus Float After HLDA
-55 C, +25 C, +125 C
o
o
o
HLDA Valid to Trailing Edge of CLK
HOLD Hold Time
-55 C, +25 C, +125 C
90
-
o
o
o
-55 C, +25 C, +125 C
0
o
o
o
HOLD Setup Time to Trailing Edge of CLK
INTR Hold Time
-55 C, +25 C, +125 C
-
300
0
o
o
o
-55 C, +25 C, +125 C
-
o
o
o
INTR, RST and TRAP Setup Time to Falling
Edge of CLK
TINS
-55 C, +25 C, +125 C
-
375
o
o
o
Address Hold Time After ALE
Trailing Edge of ALE to Leading Edge of Control
ALE Low During CLK High
ALE to Valid Data During Read
ALE to Valid Data During Write
ALE Width
TLA
TLC
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
75
150
125
675
-
-
ns
ns
ns
ns
ns
ns
ns
ns
o
o
o
-55 C, +25 C, +125 C
-
o
o
o
TLCK
TLDR
TLDW
TLL
-55 C, +25 C, +125 C
-
o
o
o
-55 C, +25 C, +125 C
-
350
-
o
o
o
-55 C, +25 C, +125 C
o
o
o
-55 C, +25 C, +125 C
200
-
o
o
o
ALE to READY Stable
TLRY
TRAE
-55 C, +25 C, +125 C
175
-
o
o
o
Trailing Edge of READ to Re-Enabling the Ad-
dress
-55 C, +25 C, +125 C
120
o
o
o
READ (or INTA) to Valid Data
TRD
TRV
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
375
550
-
-
ns
ns
o
o
o
Control Trailing Edge to Leading Edge of Next
Control
-55 C, +25 C, +125 C
o
o
o
Data Hold Time After READ INTA
READY Hold Time
TRDH
TRYH
TRYS
TWD
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 C, +25 C, +125 C
-
-
0
0
ns
ns
ns
ns
ns
o
o
o
-55 C, +25 C, +125 C
o
o
o
READY Setup Time to Leading Edge of CLK
Data Valid After Trailing Edge of WRITE
LEADING Edge of WRITE to Data Valid
NOTES:
-55 C, +25 C, +125 C
250
150
-
-
o
o
o
-55 C, +25 C, +125 C
-
o
o
o
TWDL
-55 C, +25 C, +125 C
50
1. Output timings are measured with a purely capacitive load, CL = 150pF
2. VDD = 4.75V, VIH = 4.25V, VIL = 0.8V
3. Delay times are measured with a 1MHz clock. An algorithm is used to convert the delays into the AC timings above with a TCYC = 500ns.
4. The AC table is tested as shown above to guarantee the processor system timing.
5. A8 - A15 address specifications also apply to IO/M, S0 and S1 except A8 - A15 are undefined during T4-T6 of off cycle whereas IO/M,
So, and S1 are stable.
Spec Number 518054
6
INTERSIL [ Intersil ]
