欢迎访问ic37.com |
会员登录 免费注册
发布采购

5962R9582401QXC 参数 Datasheet PDF下载

5962R9582401QXC图片预览
型号: 5962R9582401QXC
PDF下载: 下载PDF文件 查看货源
内容描述: 抗辐射的8位CMOS微处理器 [Radiation Hardened 8-Bit CMOS Microprocessor]
分类和应用: 外围集成电路微处理器时钟
文件页数/大小: 19 页 / 162 K
品牌: INTERSIL [ Intersil ]
 浏览型号5962R9582401QXC的Datasheet PDF文件第10页浏览型号5962R9582401QXC的Datasheet PDF文件第11页浏览型号5962R9582401QXC的Datasheet PDF文件第12页浏览型号5962R9582401QXC的Datasheet PDF文件第13页浏览型号5962R9582401QXC的Datasheet PDF文件第15页浏览型号5962R9582401QXC的Datasheet PDF文件第16页浏览型号5962R9582401QXC的Datasheet PDF文件第17页浏览型号5962R9582401QXC的Datasheet PDF文件第18页  
HS-80C85RH  
HS-80C85RH Caveats  
System Interface  
1. An important caveat that is applicable to CMOS devices in gen-  
eral is that unused inputs should never be left floating. This rule  
also applies to inputs connected to a tri- state bus. The need for  
external pull-up resistors during tri-state bus conditions is elimi-  
nated by the presence of regenerative latches on the following  
HS-80C85RH output pins: AD0-AD7, A8-A15, and IO/M. Figure  
10 depicts an output and corresponding regenerative latch.  
When the output driver assumes the high impedance state, the  
latch holds the bus in whatever logic state (high or low) it was be-  
fore the tri-state condition. A transient drive current of approxi-  
mately ±1.0mA at 0.5 VDD for 10nsec is required to switch the  
latch. Thus, CMOS device inputs connected to the bus are not  
allowed to float during tri-state conditions.  
The HS-80C85RH family includes memory components,  
which are directly compatible to the HS-8OC8SRH CPU. For  
example, a system consisting of the three radiation-  
hardened chips, HS-80C85RH, HS-81C56RH, and  
HS-83C55RH will have the following features:  
1. 2K Bytes ROM  
2. 256 Bytes RAM  
3. 1 Timer/Counter  
4. 4 8-bit I/O Ports  
5. 1 6-bit I/O Port  
6. 4 Interrupt Levels  
7. Serial In/Serial Out Ports  
2. The RD and WR pins of the HS-80C85RH contain internal dy-  
namic pull-up transistors to avoid spurious selection of memory  
devices when the RD and WR pins assume the high impedance  
state. This eliminates the need for external resistive pull-ups on  
these pins.  
This minimum system, using the standard I/O technique is  
as shown in Figure 12.  
In addition to standard 1/0, the memory mapped I/O offers  
an efficient I/O addressing technique. With this technique, an  
area of memory address space is assigned for I/O address,  
thereby, using the memory address for I/O manipulation.  
Figure 13 shows the system configuration of Memory  
Mapped I/O using HS-80C85RH.  
3. The RESET IN and X1 inputs on the HS-80C85RH are schmit  
trigger inputs. This eliminates the possibility of internal oscilla-  
tions in response to slow rise time input signals at these pins.  
4. A high frequency bypass capacitor of approximately 0.1 µF  
should be connected between VDD and GND to shunt power  
supply transients.  
The HS-80C85RH CPU can also interface with the standard  
radiation-hardened memory that does not have the  
multiplexed address/data bus. It will require use of the  
HS-82C12RH (8-bit latch) as shown in Figure 14.  
5. The HS-80C85RH is functional within 10 input clock cycles after  
application of power (assuming that reset has been asserted  
from power-on). Start up conditions in the crystal controlled  
oscillator mode must also account for the characteristics of the  
oscillator.  
VSS VDD  
OUTPUT  
PIN  
OUTPUT  
DRIVER  
X1  
X2  
RESET IN  
TRAP  
HOLD  
HLDA  
SOD  
SID  
REGENERATIVE  
LATCH  
RST 7.5  
RST 6.5  
RST 5.5  
INTR  
HS-80C85RH  
FIGURE 10. OUTPUT DRIVER AND LATCH FOR PINS ADO-AD7,  
A8-A15 AND IO/M.  
S1  
RESET  
OUT  
INTA  
S0  
ADDR/  
ADDR DATA ALE RD WR IO/M  
RDY CLK  
VSS VDD  
Generating An HS-80C85RH Wait State  
(8) (8)  
CE  
PORT  
(8)  
(8)  
(6)  
A
If your system requirements are such that slow memories or  
peripheral devices are being used, the circuit shown in  
Figure 11 may be used to insert one WAIT state in each  
HS-80C85RH machine cycle.  
WR  
RD  
PORT  
B
ALE  
DATA/  
ADDR  
PORT  
C
IN  
TIMER  
OUT  
IO/M  
The D flip-flops should be chosen so that:  
1. CLK is rising edge-triggered  
RESET  
2. CLEAR is low-level active.  
IOW  
RD  
ALE  
The READY line is used to extend the read and write pulse  
lengths so that the 80C85RH can be used with slow mem-  
ory. HOLD causes the CPU to relinquish the bus when it is  
through with it by floating the Address and Data Buses.  
PORT  
A
(8)  
CE  
A0-10  
DATA/  
ADDR  
TO  
PORT  
B
IO/M  
80C85RH  
CLK  
OUTPUT  
(8)  
CLEAR  
80C85RH  
READY  
INPUT  
RESET  
RDY  
CLK  
ALE †  
CLK  
CLK  
D
IOR  
VDD  
“D”  
F/F  
“D”  
F/F  
Q
Q
VDD  
D
VSS VDD  
VDD  
ALE and CLK (OUT) should be buffered if CLK  
input of latch exceeds 80C85RH IOL or IOH.  
Optional Connection  
FIGURE 12. HS-80C85RH MINIMUM SYSTEM (STANDARD I/O  
TECHNIQUE)  
FIGURE11. GENERATIONOFAWAITSTATEFORHS-80C85RH  
CPU.  
Spec Number 518054  
14  
 复制成功!