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5962R9582401QXC 参数 Datasheet PDF下载

5962R9582401QXC图片预览
型号: 5962R9582401QXC
PDF下载: 下载PDF文件 查看货源
内容描述: 抗辐射的8位CMOS微处理器 [Radiation Hardened 8-Bit CMOS Microprocessor]
分类和应用: 外围集成电路微处理器时钟
文件页数/大小: 19 页 / 162 K
品牌: INTERSIL [ Intersil ]
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HS-80C85RH  
enabled or disabled by El or Dl software instructions), and  
Functional Description  
causes the CPU to fetch in an RST instruction, externally  
placed on the data bus, which vectors a branch to any one of  
eight fixed memory locations (Restart addresses). The deci-  
mal addresses of these dedicated locations are: 0, 8, 16,  
24, 32, 40, 48, and 56. Any of these addresses may be used  
to store the first instruction(s) of a routine designed to  
service the requirements of an interrupting device. Since the  
(RST) is a call, completion of the instruction also stores the  
old program counter contents on the STACK. Each of the  
three RESTART inputs, 5.5, 6.5, and 7.5, has a programma-  
ble mask. TRAP is also a RESTART interrupt but it is  
nonmaskable.  
The HS-80C85RH is a complete 8-bit parallel central pro-  
cessing unit implemented in a self aligned, silicon gate,  
CMOS technology. Its static design allows the device to be  
operated at any external clock frequency from a maximum of  
4MHz down to DC. The processor clock can be stopped in  
either the high or low state and held there indefinitely. This  
type of operation is especially useful for system debug or  
power critical applications. The device is designed to fit into  
a minimum system of three ICs: CPU (HS-80C85RH), RAM/  
IO (HS-81C55/56RH) and ROM/IO Chip (HS-83C55RH).  
Since the HS-80C85RH is implemented in CMOS, all of the  
advantages of CMOS technology are inherent in the device.  
These advantages include low standby and operating power,  
high noise immunity, moderately high speed, wide operating  
temperature range, and designed-in radiation hardness.  
Thus the HS-80C85RH is ideal for weapons and space  
applications.  
The three maskable interrupts cause the internal execution  
of RESTART (saving the program counter in the stack and  
branching to the RESTART address) if the interrupts are  
enabled and if the interrupt mask is not set. The non-  
maskable TRAP causes the internal execution of  
a
RESTART vector independent of the state of the interrupt  
enable or masks. (See Table 9.)  
The HS-80C85RH has twelve addressable 8-bit registers.  
Four of them can function only as two 16-bit register pairs.  
Six others can be used interchangeably as 8-bit registers or  
as 16-bit register pairs. The HS-80C85RH register set is as  
follows:  
There are two different types of inputs in the restart  
interrupts. RST 5.5 and RST 6.5 are high level-sensitive and  
are recognized with the same timing as INTR. RST 7.5 is  
rising edge sensitive.  
For RST 7.5, only a pulse is required to set an internal  
flipflop which generates the internal interrupt request (a  
normally high level signal with a low going pulse is recom-  
mended for highest system noise immunity). The RST 7.5  
request flip-flop remains set until the request is serviced.  
Then it is reset automatically. This flip-flop may also be reset  
by using the SlM instruction or by issuing a RESET IN to the  
80C85RH. The RST 7.5 internal flip-flop will be set by a  
pulse on the RST 7.5 pin even when the RST 7.5 interrupt is  
masked out.  
MNEMONIC  
ACC or A  
PC  
REGISTER  
Accumulator  
CONTENTS  
8 -bits  
Program Counter  
16-bit Address  
BC, DE, HL  
General-Purpose  
Registers; Data  
Pointer(HL)  
8-bits x 6 or  
16-bits x 3  
SP  
Stack Pointer  
Flag Register  
16-bit Address  
The status of the three RST interrupt masks can only be  
affected by the SIM instruction and RESET IN.  
Flags or F  
5 Flags (8-bit space)  
The HS-80C85RH uses a multiplexed Data Bus. The The interrupts are arranged in a fixed priority that determines  
address is split between the higher 8-bit Address Bus and which interrupt is to be recognized if more than one is  
the lower 8-bit Address/Data Bus. During the first T state pending as follows: TRAP-highest priority, RST 7.5, RST  
(clock cycle) of a machine cycle the low order address is 6.5, RST 5.5, INTR-lowest priority. This priority scheme does  
sent out on the Address/Data bus. These lower 8 bits may not take into account the priority of a routine that was started  
be latched externally by the Address Latch Enable signal by a higher priority interrupt. RST 5.5 can interrupt an RST  
(ALE). During the rest of the machine cycle the data bus is 7.5 routine if the interrupts are re-enabled before the end of  
used for memory or I/O data.  
the RST 7.5 routine.  
The HS-80C85RH provides RD, WR, S0, S1, and IO/M sig- The TRAP interrupt is useful for catastrophic events such as  
nals for bus control. An Interrupt Acknowledge signal (INTA) power failure or bus error. The TRAP input is recognized just  
is also provided. HOLD and all Interrupts are synchronized as any other interrupt but has the highest priority. It is not  
with the processor’s internal clock. The HS-80C85RH also affected by any flag or mask. The TRAP input is both edge  
provides Serial Input Data (SID) and Serial Output Data and level sensitive. The TRAP input must go high and  
(SOD) lines for simple serial interface.  
remain high until it is acknowledged. It will not be recognized  
again until it goes low, then high again. This avoids any false  
triggering due to noise or logic glitches. Figure 8illustrates  
the TRAP interrupt request circuitry within the HS-80C85RH.  
Note that the servicing of any interrupt (TRAP, RST 7.5, RST  
6.5, RST 5.5, INTR) disables all future interrupts (except  
TRAPs) until an EI instruction is executed.  
In addition to these features, the HS-80C85RH has three  
maskable, vector interrupt pins, one nonmaskable TRAP  
interrupt, and a bus vectored interrupt, INTR.  
Interrupt and Serial I/O  
The HS-80C85RH has 5 interrupt inputs: INTR, RST 5.5,  
RST 6.5, RST 7.5, and TRAP INTR is maskable (can be  
Spec Number 518054  
12  
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