ISL70218SEH
Pin Configuration
Pin Descriptions
ISL70218SEH
(10 LD FLATPACK)
TOP VIEW
OUT_A
-IN_A
+IN_A
NC
1
2
3
4
5
10
9
V+
OUT_B
-IN_B
+IN_B
NC
-
+
8
+
-
7
V-
6
PIN NUMBER
PIN NAME
EQUIVALENT CIRCUIT
Circuit 2
DESCRIPTION
1
2
OUT_A
-IN_A
+IN_A
NC
Amplifier A output
Circuit 1
Amplifier A inverting input
Amplifier A non-inverting input
No connect
3
Circuit 1
4
5
V-
Circuit 1, 2, 3
Negative power supply
No connect
6
NC
7
+IN_B
-IN_B
OUT_B
V+
Circuit 1
Circuit 1
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
8
9
Circuit 2
10
Circuit 1, 2, 3
Positive power supply
V
+
V
+
V
+
CAPACITIVELY
TRIGGERED ESD
CLAMP
OUT
IN-
IN
+
V
-
V
V
-
-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
Ordering Information
ORDERING NUMBER
PART
NUMBER
TEMP RANGE
(°C)
PKG.
DWG. #
(Notes 1, 2)
PACKAGE
10 Ld Flatpack
10 Ld Flatpack
Die
5962R1222201VXC
ISL70218SEHVF
-55 to +125
-55 to +125
-55 to +125
-55 to +125
K10.A
K10.A
ISL70218SEHF/PROTO
5962R1222201V9A
ISL70218SEHX/SAMPLE
ISL70218SRHMEVAL1Z
NOTES:
ISL70218 SEHF/PROTO
ISL70218SEHVX
ISL70218SEHVX/SAMPLE
Evaluation Board
Die
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70218SEH. For more information on MSL, please see Tech Brief TB363.
FN7957.1
August 24, 2012
2
INTERSIL [ Intersil ]
