ISL7457SRH
Power Dissipation Calculation
Application Information
When switching at high speeds, or driving heavy loads, the
ISL7457SRH drive capability is limited by the rise in die
temperature brought about by internal power dissipation. For
reliable operation die temperature must be kept below
Product Description
The ISL7457SRH is a high performance, high speed quad
CMOS driver. Each channel of the ISL7457SRH consists of
a single P-channel high side driver and a single N-Channel
low side driver. These 3.5Ω devices will pull the output
T
(+150°C).
JMAX
Power dissipation may be calculated as shown in
Equation 1:
(OUTx) to either the high or low voltage, on V and V
H
L
respectively, depending on the input logic signal (INx). It
should be noted that there is only one set of high and low
voltage pins.
4
2
S
2
P
= (V × I ) +
(C
× V × f) + (C × V
× f)
OUT
(EQ. 1)
D
S
S
INT
L
∑
1
A common output enable (OE) pin is available on the
ISL7457SRH. When this pin is pulled low, it will put all
outputs in a high impedance state.
where:
is the power dissipated in the device.
Supply Voltage Range and Input Compatibility
P
D
The ISL7457SRH is designed to operate on nominal 5V to
15V supplies with ±10% tolerance. Table 1 on page 7 shows
V is the total power supply to the ISL7457SRH (from V +
S
S
to V -).
S
the specifications for the relationship between the V +, V -,
S
S
V , V , and GND pins. The ISL7457SRH does not contain a
I
is the quiescent supply current.
H
L
S
true analog switch and therefore V should always be less
than V .
H
L
C
is the internal load capacitance (80pF max).
INT
f is the operating frequency.
C is the load capacitance.
All input pins are compatible with both 3.3V and 5V CMOS
signals.
L
PCB Layout Guidelines
V
is the swing on the output (V - V ).
OUT H L
1. A ground plane must be used, preferably located on layer
#2 of the PCB.
Junction Temperature Calculation
Once the power dissipation for the application is determined,
the maximum junction temperature can be calculated as
shown in Equation 2:
2. Connect the GND and V - pins directly to the ground
S
plane.
2. The V +, V and V pins should be bypassed directly to
S
H
L
(EQ. 2)
T
= T
+ (Θ + Θ ) × P
SMAX JC CS D
JMAX
the ground plane using a low-ESR, 4.7µF solid tantalum
capacitor in parallel with a 0.1µF ceramic capacitor. Locate
all bypass capacitors as close as possible to the respective
pins of the IC.
where:
T
is the maximum operating junction temperature
JMAX
(150°C).
3. Keep all input and output connections to the IC as short as
possible.
T
is the maximum operating sink temperature of the
SMAX
PCB.
4. For high frequency operation above 1MHz, consider use
of controlled impedance traces terminated into 50Ω on all
inputs and outputs.
θ
is the thermal resistance, junction-to-case, of the
JC
package.
θ
is the thermal resistance, case-to-sink, of the PCB.
is the power dissipation calculated in Equation 1.
CS
P
D
PCB Thermal Management
To minimize the case-to-sink thermal resistance, it is
recommended that multiple vias be placed on the top layer
of the PCB directly underneath the IC. The vias should be
connected to the ground plane, which functions as a
heatsink. A gap filler material (i.e. a Sil-Pad or thermally
conductive epoxy) may be used to insure good thermal
contact between the bottom of the IC and the vias.
FN6874.0
March 16, 2009
9
INTERSIL [ Intersil ]
