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12103D226KAT2A 参数 Datasheet PDF下载

12103D226KAT2A图片预览
型号: 12103D226KAT2A
PDF下载: 下载PDF文件 查看货源
内容描述: 双路15A / 30A单降压型电源模块 [Dual 15A/Single 30A Step-Down Power Module]
分类和应用: 电源电路电容器PC
文件页数/大小: 28 页 / 1136 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
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ISL8225M
Pin Descriptions
PIN
NUMBER
21, 1
PIN
NAME
VSEN1-, VSEN2-
TYPE
I
PIN DESCRIPTION
Output voltage negative feedback. Negative input of the differential remote sense for the regulator. Connect to the
negative rail or ground of the load/processor, as shown in
The negative feedback pins can be used to
program the module operation conditions. See
and
for details.
20, 2
COMP1, COMP2 I/O Error amplifier outputs. Typically floating for dual-output use. For parallel use, a 470pF~1nF capacitor is recommended
on the COMP pins of each SLAVE phase to eliminate the coupling noise. All COMP pins of SLAVE phases need to tie to
MASTER phase COMP1 pin (first phase). Internal compensation networks are implemented for working in the full range
of I/O conditions.
MODE
I
Mode setting. Typically floating for dual-output use; tie to SGND for parallel use. See
and
for details.
When VSEN2- is pulled within 700mV of VCC, the 2nd channel’s remote sensing amplifier is disabled. The MODE pin,
as well as the VSEN2+ pin, determine relative phase-shift between the two channels and the CLKOUT signal output.
3
18, 4
VMON1, VMON2 I/O Remote sensing amplifier outputs. These pins are connected internally to OV/UV/PGOOD comparators, so they can’t
be floated when the module works in multi-phase operation. When VSEN1-, VSEN2- are pulled within 700mV of VCC,
the corresponding remote sensing amplifier is disabled; the output (VMON pin) is in high impedance. In this event, the
VMON pins can be used as an additional monitor of the output voltage, with a resistor divider to protect the system
against single point of failure. The default setting voltage is 0.6V. See
for details.
SYNC
I
Signal synchronization. An optional external resistor (R
SYNC
) connected from this pin to SGND increases oscillator
switching frequency (Figure
and
The internal default frequency is 500kHz with this pin floating. Also, the
internal oscillator can lock to an external frequency source or the CLKOUT signal from another ISL8225M. Input voltage
range for external source: 3V to 5V square wave. No capacitor is recommended on this pin.
5
6
7
14, 8
9, 13
12, 10
SGND
VCC
VIN1, VIN2
PGND
PHASE1,
PHASE2
NC
EN/FF1,
EN/FF2
PWR Control signal ground.
Connect to PGND under the module in the quiet inner layer. Make sure to have the single location
for the connection between SGND and PGND to avoid noise coupling. See “Layout Guide” on page 23.
PWR 5V internal linear regulator output. Voltage range: 3V to 5.6V. The decoupling ceramic capacitor for the VCC pin is
recommended to be 4.7µF.
PWR Power inputs. Input voltage range: 4.5V to 20V. Tie directly to the input rail. VIN1 provides power to the internal linear
drive circuitry. When the input is 4.5V to 5.5V, VIN should be tied directly to VCC.
PWR Power ground. Power ground pins for both input and output returns.
PWR Phase node. Use for monitoring switching frequency. Phase pins should be floating or used for snubber connections.To
achieve better thermal performance, the phase planes can also be used for heat removal with thermal vias connected
to large inner layers.
-
Non-connection pin. This pin is floating with no connection inside.
I/O Enable and feed-forward control. Tie a resistor divider to VIN or use the system enable signal for this pin. The voltage
turn-on threshold is 0.8V. With a voltage lower than the threshold, the corresponding channel can be disabled
independently. By connecting to VIN with a resistor divider, the input voltage can be monitored for UVLO (under-voltage
lockout) function. The voltage on each EN/FF pin is also used to adjust the internal control loop gain independently to
realize the feed-forward function. Please set the EN/FF between 1.25V to 5V. A 1nF capacitor is recommended on each
EN/FF pin. Please see
to select resistor divider and application details in “EN/FF Turn ON/OFF” on page 19.
I/O Clock out. Provide the clock signal for the input synchronization signal of other ISL8225Ms. Typically tied to VCC for
dual-output use with 180° phase-shift. See
and
when using more than one ISL8225M. When the
module is in dual-output mode, the clock-out signal is disabled. By programming the voltage level of this CLKOUT pin,
the module can work for DDR/tracking or as two independent outputs with selectable phase-shift. See
O
Current sharing control. Tie all ISHARE pins together when multiple modules are configured for current sharing and
share a common current output. The ISHARE voltage represents the average current of all active and connected
channels. A 470pF capacitor is recommended for each ISHARE pin for multiple phase applications. Typically, the
ISHARE pin should be floating for dual-output or single module application.
Output voltage positive feedback. Positive inputs of differential remote sense for the regulator. A resistor divider can
be connected to this pin to program the output voltage. It is recommended to put the resistor divider close to the
module and connect the kelvin sensing traces of VOUT and VSEN- to the sensing points of the load/processor; see
The VSEN2+ pin can be used to program the module operation conditions. See
and
for
details.
Power good. Provide open-drain power-good signal when the output is within 9% of the nominal output regulation point
with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs (VMON) of the internal differential
amplifiers.
11
15, 16
17
CLKOUT
19
ISHARE
22, 26
VSEN1+,
VSEN2+
I
23, 25
24
VOUT1, VOUT2 PWR Power Output. Apply output load between these pins and PGND pins. Output voltage range: 0.6V to 6V.
PGOOD
O
5
FN7822.1
January 31, 2013