ISL8225M
Tracking Function
Layout Guide
If CLKOUT is less than 800mV, an external soft-start ramp (0.6V)
can be in parallel with the Channel 2 internal soft-start ramp for
tracking applications. Therefore, the Channel 2’s output voltage
can track the output voltage of Channel 1.
To achieve stable operation, low losses, and good thermal
performance, some layout considerations are necessary
(Figure 32).
• VOUT1, VOUT2, PHASE1, PHASE2, PGND, VIN1 and VIN2
should have large, solid planes. Place enough thermal vias to
connect the power planes in different layers under or around
the module.
The tracking function can be applied to a typical Double Data
Rate (DDR) memory application, as shown in Figure 20 on
page 13. The output voltage (typical VTT output) of Channel 2
tracks with the input voltage [typical VDDQ*(1+k) from
Channel 1] at the CLKOUT pin. As for the external input signal
and the internal reference signal (ramp and 0.6V), the one with
the lowest voltage is used as the reference for comparing with
the FB signal. In DDR configuration, VTT channel should start up
later, after its internal soft-start ramp, such that VTT tracks the
voltage on the CLKOUT pin derived from VDDQ. This configuration
can be achieved by adding more filtering at EN/FF1 than at
EN/FF2.
• Place high-frequency ceramic capacitors between VIN, VOUT,
and PGND, as closely to the module as possible in order to
minimize high-frequency noise.
• Use remote sensed traces to the regulation point to achieve
tight output voltage regulation, and keep the sensing traces
close to each other in parallel.
• PHASE1 and PHASE2 pads are switching nodes that generate
switching noise. Keep these pads under the module. For
noise-sensitive applications, it is recommended to keep phase
pads only on the top and inner layers of the PCB. Also, do not
place phase pads exposed to the outside on the bottom layer
of the PCB.
The resistor divider ratio (k) of R7/R8 in Figure 20 is calculated
as shown in Equation 7:
V
TT
(EQ. 7)
------------
k =
– 1
0.6V
• Avoid routing any noise-sensitive signal traces, such as the
VSEN+, VSEN-, ISHARE, COMP and VMON sensing points, near
the PHASE pins.
Mode Programming
ISL8225M can be programmed for dual-output, paralleled
single-output or mixed outputs (Channel 1 in parallel and
Channel 2 in dual-output). With multiple ISL8225Ms, up to 6
modules using its internal cascaded clock signal control, the
modules can supply large current up to 180A. For complete
operation, please refer to Table 3 on page 18. Commonly used
settings are listed in Table 5.
• Use a separated SGND ground copper area for components
connected to signal ground pins. Connect SGND to PGND with
multiple vias underneath the unit in one location to avoid the
noise coupling, as shown in Figure 32. Don't ground vias
surrounded by the noisy planes of VIN, PHASE and VOUT. For
dual output applications, the SGND to PGND vias are preferred
to be as close as possible to SGND pin.
TABLE 5. PHASE-SHIFT SETTING
• Optional snubbers can be put on the bottom side of the board
layout, connecting the PHASE to PGND planes, as shown in
Figure 32.
PHASE-SHIFT
OPERATION
BETWEEN PHASES VSEN2- VSEN2+ CLKOUT MODE
Dual Output
(Figure 18)
180°
180°
90°
N/C
VCC
VCC
VCC
N/C
N/C
VCC
N/C
VCC
N/C
N/C
N/C
N/C
SGND
VCC
COUT2
COUT1
PGND
R3
PGND
R1
30A
(Figure 19)
VOUT2
VOUT1
+
-
+
-
TO LOAD
R4
TO LOAD
R2
60A
(Figure 22)
KELVIN CONNECTIONS
FOR THE VSENS LINES
KELVIN CONNECTIONS
FOR THE VSENS LINES
PIN 1
90A
60°
SGND
(Figure 24)
SGND
VIN2
VIN1
When the module is in the dual-output condition, depending
upon the voltage level at CLKOUT (which is set by the VCC resistor
divider output), ISL8225M operates with phase shifted as the
CLKOUT voltage shown in Table 6. The phase shift is latched as
CIN2
CIN1
PHASE2
PHASE1
V
rises above POR; it cannot be changed on the fly.
CC
OPTIONAL SNUBBER
OPTIONAL SNUBBER
TABLE 6. CLKOUT TO PROGRAM PHASE SHIFT AT DUAL-OUTPUT
CLKOUT
VOLTAGE SETTING
PHASE FOR CLKOUT WRT RECOMMENDED
PGND
CHANNEL 1
CLKOUT VOLTAGE
<29% of V
CC
-60°
15% V
37% V
53% V
CC
CC
CC
FIGURE 32. RECOMMENDED LAYOUT
29% to 45% of V
90°
CC
CC
45% to 62% of V
120°
62% of V
CC
180°
V
CC
FN7822.1
January 31, 2013
23
INTERSIL [ Intersil ]
