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12103D226KAT2A 参数 Datasheet PDF下载

12103D226KAT2A图片预览
型号: 12103D226KAT2A
PDF下载: 下载PDF文件 查看货源
内容描述: 双路15A / 30A单降压型电源模块 [Dual 15A/Single 30A Step-Down Power Module]
分类和应用: 电源电路电容器PC
文件页数/大小: 28 页 / 1136 K
品牌: INTERSIL [ Intersil ]
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ISL8225M  
commonly used conditions. Otherwise, use the following procedures  
to finish the EN/FF design:  
Functional Description  
Initialization  
1. A resistor divider from V to GND is recommended to set the  
IN  
EN/FF voltage between 1.25V to 5.0V. The resistor divider  
ratio is recommended to be between 3/1 to 4/1 (as shown in  
Figure 21) with a resistor divider at 7.15k/2.05k.  
Initially, the Power-On Reset (POR) circuits continuously monitor  
bias voltages (V ) and voltage at the EN/FF pin. The POR  
CC  
function initiates soft-start operation 384 clock cycles  
after: (1) the EN pin voltage is pulled above 0.8V, (2) all input  
supplies exceed their POR thresholds, and (3) the PLL locking  
time expires. The Enable pin can be used as a voltage monitor  
and to set the desired hysteresis, with an internal 30µA sinking  
current going through an external resistor divider. The sinking  
current is disengaged after the system is enabled. This feature is  
specially designed for applications that require higher input rail  
POR for better under-voltage protection. For example, in 12V  
2. Check EN turn-on hysteresis (Recommend V  
> 0.3V) :  
(EQ. 4)  
EN_HYS  
5  
V
= N R 3x10  
UP  
EN HYS  
where:  
• R is the top resistor of the resistor divider  
UP  
• N is the total number of the EN/FF pins tied to the resistor divider  
3. Set the maximum current flowing through the top pull-up  
applications, R = 53.6kand R  
turn-on threshold (V  
EN_RTH  
= 5.23ksets the  
UP  
DOWN  
) to 10.6V and the turn-off threshold  
).  
resistor R to below 7mA (considering EN/FF is pulled to  
UP  
ground (V  
= 0)). Refer to Figure 23; a 3.01k/1kΩ  
EN/FF  
(V  
) to 9V, with 1.6V hysteresis (V  
EN_FTH EN_HYS  
resistor is used to allow for the input voltage from 5V to 20V  
operation. In addition, the maximum current flowing through  
R5 is 6.6mA (<7mA).  
During shutdown or fault conditions, soft-start is quickly reset,  
and the gate driver immediately changes state (<100ns) when  
input drops below POR.  
4. If the EN/FF is controlled by system EN signal instead of the  
input voltage, we recommend setting the fixed EN/FF voltage  
to about 1/3.5 of the input voltage. If the input voltage is 12V,  
a 3.3V system EN signal can be tied to EN/FF pin directly.  
Enable and Voltage Feed-forward  
Voltage applied to the EN/FF pin is fed to adjust the sawtooth  
amplitude of the channel. Sawtooth amplitude is set to 1.25 times  
the corresponding FF voltage when the module is enabled. This  
configuration helps maintain a constant gain. This configuration  
also helps maintain input voltage to achieve optimum loop response  
over a wide input voltage range.  
5. If the input voltage is below 5.5V, it is recommended to have  
EN/FF voltage >1.5V to have better stability. The input voltage  
can be directly tied to the VCC pin to disable the internal LDO.  
6. A 1nF capacitor is recommended on the EN/FF pin to avoid  
the noise injecting into the feed-forward loop.  
A 384-cycle delay is added after the system reaches its rising  
POR and prior to soft-start. The RC timing at the FF pin should be  
small enough to ensure that the input bus reaches its static state  
and that the internal ramp circuitry stabilizes before soft-start. A  
large RC could cause the internal ramp amplitude not to  
synchronize with the input bus voltage during output start-up or  
when recovering from faults. A 1nF capacitor is recommended as  
a starting value for typical applications.  
Thermal Considerations  
The ISL8225M QFN package offers typical junction to ambient  
thermal resistance θ of approximately 10°C/W at natural  
JA  
convection (~5.8°C/W at 400LFM) with a typical 4-layer PCB.  
Therefore, use Equation 5 to estimate the module junction  
temperature:  
(EQ. 5)  
T
= P × Θ + T  
junction  
jA ambient  
In a multi-module system, with the EN pins are wired together, all  
modules can immediately turn off, at one time, when a fault  
condition occurs in one or more modules. A fault pulls the EN pin  
low, disabling all modules, and does not create current bounce;  
thus, no single channel is overstressed when a fault occurs.  
where:  
• T  
is the module internal maximum temperature (°C)  
is the system ambient temperature (°C)  
junction  
• T  
ambient  
• P is the total power loss of the module package (W)  
Because the EN pins are pulled down under fault conditions, the  
θ is the thermal resistance of module junction to ambient  
JA  
pull-up resistor (R ) should be scaled to sink no more than 7mA  
UP  
current from the EN pin. Essentially, the EN pins cannot be  
directly connected to VCC.  
If the calculated temperature, T  
design target, the extra cooling scheme is required. Please refer  
to “Current Derating” on page 24 for adding air flow.  
, is over the required  
junction  
VIN  
R
² V  
V
EN_HYS  
UP  
= --------------------------------------------------------------  
EN_REF  
V  
R
V
= ----------------------------  
R
UP  
DOWN  
I
V
R
EN_HYS  
UP  
EN_FTH  
EN_REF  
384  
0.8V  
CLOCK  
EN  
SOFT-START  
= V  
V  
CYCLES  
EN_FTH  
EN_RTH  
EN_HYS  
ON/OFF  
R
DOWN  
I
= 30µA  
EN_HYS  
OV, OT, OC, AND PLL LOCKING FAULTS  
FIGURE 26. SIMPLIFIED ENABLE AND VOLTAGE FEED-FORWARD CIRCUIT  
FN7822.1  
January 31, 2013  
20  
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