28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Number
Description
-001
Original version
Section 3.4, V Program and Erase Voltages, added
PP
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
-002
I
maximum specification change from ±25 µA to ±50 µA
PPR
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V V read specification (Section 3.4)
PP
Removed 120 ns and 150 ns speed offerings
-003
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A –A = 0 when in read identifier mode (Section 3.2.2)
1
20
Status register clarification for SR3 (Table 7)
V
and V absolute maximum specification = 3.7 V (Section 4.1)
CC
CCQ
Combined I
Combined I
and I
into one specification (Section 4.4)
into one specification (Section 4.4)
PPW
PPE
CCW
and I
CCE
Max Parameter Block Erase Time (t
/t
) reduced to 4 sec (Section 4.7)
) reduced to 5 sec (Section 4.7)
) changed to 5 µs typical and 20 µs maximum
WHQV2 EHQV2
/t
/t
-004
Max Main Block Erase Time (t
Erase suspend time @ 12 V (t
(Section 4.7)
WHQV3 EHQV3
WHRH2 EHRH2
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA package diagrams corrected (Figures 3 and 4)
I
test conditions corrected (Section 4.4)
PPD
-005
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
V
and V Specification change (Section 4.4)
IH
IL
I
test conditions clarification (Section 4.4)
CCS
Added Command Sequence Error Note (Table 7)
Datasheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
-006
-007
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in Ordering Information
3UHOLPLQDU\
v
INTEL [ INTEL ]
