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TE28F160C3BA90 参数 Datasheet PDF下载

TE28F160C3BA90图片预览
型号: TE28F160C3BA90
PDF下载: 下载PDF文件 查看货源
内容描述: 高级+引导块闪存( C3 ) [Advanced+ Boot Block Flash Memory (C3)]
分类和应用: 闪存
文件页数/大小: 68 页 / 1132 K
品牌: INTEL [ INTEL ]
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Intel Advanced+ Boot Block Flash Memory (C3)  
The 12 V V mode enhances programming performance during the short period of time typically  
PP  
found in manufacturing processes; however, it is not intended for extended use. 12 V may be  
applied to VPP during Program and Erase operations for a maximum of 1000 cycles on the main  
blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80  
hours maximum. Stressing the device beyond these limits may cause permanent damage.  
4.2.2  
Suspending and Resuming Program  
The Program Suspend command halts an in-progress program operation so that data can be read  
from other locations of memory. Once the programming process starts, issuing the Program  
Suspend command to the CUI requests that the WSM suspend the program sequence at  
predetermined points in the program algorithm. The device continues to output status-register data  
after the Program Suspend command is issued. Polling status-register bits SR[7] and SR[2] will  
determine when the program operation has been suspended (both will be set to “1”). t  
/
WHRH1  
t
specify the program-suspend latency.  
EHRH1  
A Read-Array command can now be issued to the CUI to read data from blocks other than that  
which is suspended. The only other valid commands while program is suspended are Read Status  
Register, Read Identifier, CFI Query, and Program Resume.  
After the Program Resume command is issued to the flash memory, the WSM will continue with  
the programming process and status register bits SR[2] and SR[7] will automatically be cleared.  
The device automatically outputs status register data when read (see Figure 14, “Program Suspend  
/ Resume Flowchart” on page 53) after the Program Resume command is issued. V must remain  
PP  
at the same V level used for program while in program-suspend mode. RP# must also remain at  
PP  
V .  
IH  
4.3  
Erase Mode  
To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI, along with an  
address identifying the block to be erased. This address is latched internally when the Erase  
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only  
one block can be erased at a time. The WSM will execute a sequence of internally timed events to  
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all  
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”  
When the status register indicates that erasure is complete, check the erase-status bit to verify that  
the Erase operation was successful. If the Erase operation was unsuccessful, SR[5] of the status  
register will be set to a “1,” indicating an erase failure. If V was not within acceptable limits after  
PP  
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,  
SR[5] of the status register is set to indicate an erase error, and SR[3] is set to a “1” to identify that  
V
supply voltage was not within acceptable limits.  
PP  
After an Erase operation, clear the status register (0x50) before attempting the next operation. Any  
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status-  
register reads, it is advisable to place the flash in read-array mode after the erase is complete.  
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Datasheet