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Intel Advanced+ Boot Block Flash Memory (C3)
3.1.4
3.1.5
Standby
Deselecting the device by bringing CE# to a logic-high level (V ) places the device in standby
IH
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during a Program or Erase operation, the device continues to consume active power
until the Program or Erase operation is complete.
Reset
From read mode, RP# at V for time t
impedance state, and turns off all internal circuits. After return from reset, a time t
deselects the memory, places output drivers in a high-
IL
PLPH
is required
PHQV
until the initial read-access outputs are valid. A delay (t
or t
) is required after return from
PHWL
PHEL
reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored.
The CUI resets to read-array mode, the status register is set to 0x80, and all blocks are locked. See
Figure 10, “Reset Operations Waveforms” on page 48.
If RP# is taken low for time t
during a Program or Erase operation, the operation will be
PLPH
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process which takes time
t
to complete.
PLRH
2. After time t
enter reset mode (if RP# is deasserted after t
on page 48.
, the part will either reset to read-array mode (if RP# is asserted during t
) or
PLRH
PLRH
). See Figure 10, “Reset Operations Waveforms”
PLRH
In both cases, after returning from an aborted operation, the relevant time t
must be observed before a Read or Write operation is initiated, as discussed in the previous
or t
/t
PHWL PHEL
PHQV
paragraph. However, in this case, these delays are referenced to the end of t
RP# goes high.
rather than when
PLRH
As with any automated device, it is important to assert RP# during a system reset. When the system
comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or Block-Erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the
flash memory may be providing status information instead of array data. Intel® Flash memories
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
18
Datasheet
INTEL [ INTEL ]
