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Intel Advanced+ Boot Block Flash Memory (C3)
3.0
Device Operations
The C3 device uses a CUI and automated algorithms to simplify Program and Erase operations.
The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and
programming.
The internal WSM completely automates Program and Erase operations while the CUI signals the
start of an operation and the status register reports device status. The CUI handles the WE#
interface to the data and address latches, as well as system status requests during WSM operation.
3.1
Bus Operations
The C3 device performs read, program, and erase operations in-system via the local CPU or
microcontroller. Four control pins (CE#, OE#, WE#, and RP#) manage the data flow in and out of
the flash device. Table 5 on page 17 summarizes these bus operations.
Table 5. Bus Operations
Mode
RP#
CE#
OE#
WE#
DQ[15:0]
Read
Write
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
X
VIL
VIH
VIH
X
VIH
VIL
VIH
X
DOUT
DIN
Output Disable
Standby
High-Z
High-Z
High-Z
Reset
X
X
NOTE: X = Don’t Care (VIL or VIH
)
3.1.1
Read
When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted.
CE# is the device selection control; when active low, it enables the flash memory device. OE# is
the data output control; when low, data is output on DQ[15:0]. See Figure 8, “Read Operation
Waveform” on page 42.
3.1.2
Write
A write cycle occurs when both CE# and WE# are low; RP# and OE# are high. Commands are
issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory
location. Address and data are latched on the rising edge of the WE# or CE# pulse, whichever
occurs first. See Figure 9, “Write Operations Waveform” on page 47.
3.1.3
Output Disable
With OE# at a logic-high level (V ), the device outputs are disabled. DQ[15:0] are placed in a
IH
high-impedance state.
Datasheet
17
INTEL [ INTEL ]
