ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Standard I/O Card
Interface Signal Name
DMA-Capable Card Interface
When Signal Redefinition for DMA Interface
is Effective
Signal Usage
-IOIS16 or may be selected as the active-low
DMA request input
-IOIS16
Extension Control 1 register bits 7-6 = ‘10’
Extension Control 1 register bits 7-6 = ‘11’
Extension Control 1 register bits 7-6 = ‘01’
(BVD2/)
-SPKR/-LED
-SPKR/-LED or may be selected as the active-
low DMA request input
-INPACK or may be selected as the active-low
DMA request input
-INPACK
-REG
-OE
-REG during standard cycles, active-high
DACK during DMA read/write cycles
Only during actual card DMA read or write
cycle
-OE during standard cycles, active-low -TC
during DMA write cycles
During DMA write cycles (that is, when -REG is
high and -IORD is low)
-WE during standard cycles, active-low -TC
during DMA read cycles
During DMA read cycles (that is, when -REG is
high and -IOWR is low)
-WE
Figure 17. Card DMA Request and Acknowledge Handshake with Terminal Count
PD6722
PC Card
-DREQ
-IOIS16, -SPKR, or -INPACK
-IOIS16, -SPKR, or -INPACK
DACKa
-TC
-REG
-REG
-OE/-WE
-OE/-WE
a A DMA cycle is the DMA acknowledge to the card.
Notice that the DMA acknowledge to the card as -REG high is only active during the actual DMA
read or write card cycle. This means there is no mechanism to deassert DACK to the card: The card
must understand that receiving the first DMA cycle is its DMA acknowledgment.
15.4.2
15.4.3
Configuring the Socket Interface for I/O
For DMA support, bit 5 of the Interrupt and General Control register must be set to ‘1’ to put the
card interface in I/O Card Interface mode.
Preventing Dual Interpretation of DMA Handshake Signals
If the WP/-IOIS16 pin is being used as the DMA request line, the following should be considered:
1. Bit 4 of the Interface Status register is now the level of the DMA request line from the card.
2. Bit 5 of the socket’s two I/O Window Control registers should be set to ‘0’.
If a socket’s BVD2/-SPKR pin is being used as the DMA request line, speaker or LED output from
that socket is not available.
If -INPACK is selected as the DMA request input, then bit 7 of the Misc Control 1 register should
be set to ‘0’ to disable use of this signal as input acknowledge control.
Datasheet
99
INTEL [ INTEL ]
