PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
No other register bits require special settings to accommodate DMA support on a socket interface.
15.4.4
15.4.5
Turning On DMA System
The DMA System bit (bit 6 of the Misc Control 2 register) should be programmed to ‘1’ to allow
DMA operation and to redefine ISA bus interface pins for DMA support as in Figure 16.
The DMA Transfer Process
As soon as the selected DMA request input from the card becomes active (low) and the FIFO
empties, IRQ10 becomes active (high), signifying a DMA request to the system. The system then
responds with an active (low) -DACK at IRQ9, which enables the PD6722 to decode any ISA bus
DMA transfers that may occur and perform the corresponding transfers at the card. Normal card I/
O or memory reads or writes may be interspersed with DMA read and write cycles.
15.4.6
Terminal Count to Card at Conclusion of Transfer
At the conclusion of each transfer process, systems send active (high) TC (terminal count) pulses to
the -VPP_VALID pin during the last DMA cycles to the PD6722.
For a DMA write cycle, TC active is signaled at the socket interface as the -OE pin going low
during DMA-type read cycles from the PC Card.
For a DMA read cycle, TC active is signaled as the -WE pin going low during DMA-type write
cycles to the PC Card.
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Datasheet
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