PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Bit 5 — Three-State Bit 7
0
Normal operation.
For socket I/O at address 03F7h and 0377h, do not drive bit 7.
1
This bit enables floppy change bit compatibility.
Bit 6 — DMA System (PD6722 only)
0
1
Configured for non-DMA mode on the PD6722.
Configured for DMA mode on the PD6722.
On the PD6710, this bit is reserved.
On the PD6722, this bit is used to configure system interface signals for normal or DMA operation.
At reset, the signals IRQ9, IRQ10, and -VPP_VALID are in non-DMA mode, and this bit is set to
‘0’. When this bit is set to ‘1’, the IRQ9, IRQ10, and -VPP_VALID pins are reconfigured for
system bus DMA interfacing. Refer to “DMA Operation (PD6722 only)” on page 97 for a
functional description of these pins during DMA operation.
Bit 7 — IRQ15 Is RI Out
0
1
Normal IRQ15 operation.
IRQ15 is connected to Ring Indicate pin on the host processor.
This bit determines the function of the IRQ15 pin. When configured for ring indicate, IRQ15 is
used to resume a processor with NMI or SMI such as an 82486SL when a high-to-low change is
detected on the -STSCHG pin.
10.4
Chip Information
Register Name: Chip Information
Index: 1Fh
Register Per: chip
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
R:n3
PC Card Controller Identifi-
cation
Dual/Single
Socket*
PD67XX Revision Level
R:nnnn2
R:11
R:n1
1. The value for PD6710 is ‘0’, and the value for PD6722 is ‘1’.
2. This read-only value depends on the revision level of the PD67XX chip.
3. The value for PD6722 is ‘1’. The value for the PD6710 is ‘0’.
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Datasheet
INTEL [ INTEL ]
