PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
10.2
FIFO Control
Register Name: FIFO Control
Index: 17h
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Empty Write
FIFO
Scratchpad Bitsa
RW
RW:0000000
1. Because a write will flush the FIFO, these scratchpad bits should be used only when card activity is guaranteed not to occur.
a.
Bit 7 — Empty Write FIFO
Value
I/O Read
I/O Write
0
1
FIFO not empty
FIFO empty
No operation occurs; default on reset
Flush the FIFO
This bit controls FIFO operation and reports FIFO status. When this bit is written to ‘1’, all data in
the FIFO is lost. During read operations when this bit is ‘1’, the FIFO is empty. During read
operations when this bit is ‘0’, data is still in the FIFO. This bit is used to ensure the FIFO is empty
before changing timing registers.
FIFO contents will be lost whenever any of the following occur:
• PWRGOOD pin ( Table 1) is ‘0’.
• The card is removed.
• VCC Power bit (see “Bit 4 — VCC Power” on page 50) is programmed to ‘0’.
10.3
Misc Control 2
Register Name: Misc Control 2
Index: 1Eh
Register Per: chip
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
5V Core
RW:0
Bit 2
Suspend
RW:0
Bit 1
Bit 0
Low-Power
Dynamic
Mode
Bypass
Frequency
Synthesizer
Three-State
Bit 7
IRQ15 Is RI
Out
DMA System
(PD6722)
Drive LED
Enable
RW:0
RW:0
RW:0
RW:0
RW:1
RW:0
72
Datasheet
INTEL [ INTEL ]
