PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
Table 11. Index Registers (Sheet 3 of 3)
Index Value
Page
Number
Register Name
Chapter
Socket A
Socket B1
Extended Index:3
2Eh
6Eh
77
Scratchpad
Data Mask 0
Data Mask 1
Extension Control 1 (formerly DMA Control)
Maximum DMA Acknowledge Delay
Reserved
External Data
Extension Control 2
Extended index 00h
–
Extended index 01h
Extended index 02h
Extended index 03h
Extended index 04h
Extended index 05h–09h
Extended index 0Ah
‘Extended index 0Bh
77
78
78
79
–
“Extension
Registers” on
page 70
81
83
Extended Data
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
77
64
65
66
66
62
68
62
62
62
62
84
85
86
84
85
86
System Memory Map 4 Start Address Low
System Memory Map 4 Start Address High
System Memory Map 4 End Address Low
System Memory Map 4 End Address High
Card Memory Map 4 Offset Address Low
Card Memory Map 4 Offset Address High
Card I/O Map 0 Offset Address Low
Card I/O Map 0 Offset Address High
Card I/O Map 1 Offset Address Low
Card I/O Map 1 Offset Address High
Setup Timing 0
“Memory Window
Mapping Registers”
on page 64
“I/O Window
Mapping Registers”
on page 58
Command Timing 0
Recovery Timing 0
“Timing Registers” on
page 84
Setup Timing 1
Command Timing 1
Recovery Timing 1
1. Socket B is available on the dual-socket PD6722.
2. This register affects both sockets (it is not specific to either socket).
3. These registers are not available on the PD6710.
6.2
Data
Register Name: Data
Register Per: chip
Index: n/a
Register Compatibility Type 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data
44
Datasheet
INTEL [ INTEL ]
