PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
.
Figure 10. Device/Socket/Register Index Space
FFh
Socket D Registers
Possible with two PD67XXs
Socket C Registers
Socket B Registers
Socket A Registers
80h
7Fh
40h
3Fh
00h
When viewed as a 8-bit value, the contents of the Index register completely specify a single
internal-register byte. For example, when the value of this register is in the range 00h–3Fh, a
Socket A register is selected (Socket Index bit is ‘0’), and when the value of this register is in the
range 40h–7Fh, a Socket B register is selected (Socket Index bit is ‘1’). This register only reads
back for Device 0. Device 1 will read back only the upper data byte when 16-bit reads occur at
3E0h.
The internal register that is accessed when the CPU reads or writes the Data register is determined
by the current value of the Index register, as follows:
Table 11. Index Registers (Sheet 1 of 3)
Index Value
Socket B1
Page
Number
Register Name
Chapter
Socket A
Chip Revision
00h2
46
47
48
51
52
54
55
58
59
60
60
61
59
60
60
61
Interface Status
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
Power Control
“Chip Control
Registers” on
page 46
Interrupt and General Control
Card Status Change
Management Interrupt Configuration
Mapping Enable
I/O Window Control
System I/O Map 0 Start Address Low
System I/O Map 0 Start Address High
System I/O Map 0 End Address Low
System I/O Map 0 End Address High
System I/O Map 1 Start Address Low
System I/O Map 1 Start Address High
System I/O Map 1 End Address Low
System I/O Map 1 End Address High
1. Socket B is available on the dual-socket PD6722.
“I/O Window
Mapping Registers”
on page 58
2. This register affects both sockets (it is not specific to either socket).
3. These registers are not available on the PD6710.
42
Datasheet
INTEL [ INTEL ]
