3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.9
SRAM AC Characteristics—Read Operations
Table 17. SRAM AC Characteristics—Read Operations(1)
Density
Voltage Range
Note
2/4/8-Mbit
#
Sym
Parameter
2.7 V– 3.3 V
Unit
Min
Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Output Delay
70
70
35
70
–
AA
t
S-CS1#, S-CS2 to Output Delay
S-OE# to Output Delay
–
CO1, CO2
–
OE
BA
S-UB#, LB# to Output Delay
S-CS1#, S-CS2 to Output in Low Z
S-OE# to Output in Low Z
–
, t
2,3
3
5
LZ1 LZ2
0
–
OLZ
, t
S-CS1#, S-CS2 to Output in High Z
S-OE# to Output in High Z
2,3,4
3,4
0
25
25
HZ1 HZ2
0
OHZ
Output Hold from Address, S-CS1#,
R10
t
S-CS2, or S-OE# Change, Whichever Occurs
First
0
–
ns
OH
R11
R12
t
t
S-UB#, S-LB# to Output in Low Z
S-UB#, S-LB# to Output in High Z
3
3
0
0
–
ns
ns
BLZ
25
BHZ
NOTE:
1. See Figure 9, “AC Waveform: SRAM Read Operations” on page 36.
2. At any given temperature and voltage condition, t (Max) is less than and t (Max) both for a given
HZ
LZ
device and from device to device interconnection.
3. Sampled, but not 100% tested.
4. Timings of t and t are defined as the time at which the outputs achieve the open circuit conditions
HZ
OHZ
and are not referenced to output voltage levels.
Datasheet
35
INTEL [ INTEL ]
