3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 7. AC Waveform: Flash Program and Erase Operations
A
B
C
D
E
F
VIH
ADDRESSES [A]
CE#(WE#) [E(W)]
AIN
AIN
VIL
VIH
W8
(Note 1)
W5
VIL
VIH
W6
W2
OE# [G]
VIL
VIH
W9
(Note 1)
WE#(CE#) [W(E)]
VIL
W3
W4
W7
VIH
VIL
High Z
W1
Valid
SRD
DATA [D/Q]
DIN
DIN
DIN
VIH
VIL
VIH
RP# [P]
WP#
VIL
W10
W11
VPPH
2
VPPH
VPPLK
VIL
1
V
[V]
PP
NOTES:
1. F-CE# must be toggled low when reading Status Register Data. F-WE# must be inactive (high) when reading
Status Register Data.
A. F-VCC Power-Up and Standby.
B. Write Program or Erase Setup Command.
C. Write Valid Address and Data (for Program) or Erase Confirm Command.
D. Automated Program or Erase Delay.
E. Read Status Register Data (SRD): reflects completed program/erase operation.
F. Write Read Array Command.
Datasheet
33
INTEL [ INTEL ]
