3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.10
SRAM AC Characteristics—Write Operations
Table 18. SRAM AC Characteristics—Write Operations(1,2)
Density
Volt
2/4/8-Mbit
#
Sym
Parameter
2.7 V – 3.3 V
Unit
Note
Min
Max
W1
W2
t
t
Write Cycle Time
70
0
–
–
ns
ns
WC
Address Setup to S-WE# (S-CS1#) and S-UB#,
S-LB# Going Low
3
4
AS
W3
W4
W5
W6
t
t
t
t
S-WE# (S-CS1#) Pulse Width
55
30
60
60
–
–
–
–
ns
ns
ns
WP
DW
AW
CW
Data to Write Time Overlap
Address Setup to S-WE# (S-CS1#) Going High
S-CE# (S-WE#) Setup to S-WE# (S-CS1#) Going
High
ns
W7
W8
W9
t
t
t
Data Hold Time from S-WE# (S-CS1#) High
Write Recovery
0
0
–
–
–
ns
ns
DH
WR
BW
5
S-UB#, S-LB# Setup to S-WE# (S-CS1#) Going
High
60
ns
NOTES:
1. See Figure 10, “AC Waveform: SRAM Write Operations” on page 38.
2. A write occurs during the overlap (t ) of low S-CS1# and low S-WE#. A write begins when S-CS1# goes
WP
low and S-WE# goes low with asserting S-UB# or S-LB# for single byte operation or simultaneously
asserting
S-UB# and S-LB# for double byte operation. A write ends at the earliest transition when S-CS1# goes high
and S-WE# goes high. The t
is measured from the beginning of write to the end of write.
WP
3. t is measured from the address valid to the beginning of write.
AS
4. t
5. t
is measured from S-CS1# going low to end of write.
is measured from the end of write to the address change. t
WP
WR
applied in case a write ends as S-CS1#
WR
or S-WE# going high.
Datasheet
37
INTEL [ INTEL ]
