3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
7.0
System Design Considerations
This section contains information that would have been contained in a product design guide in
earlier generations. In an effort to simplify the amount of documentation, relevant system design
considerations have been combined into this document.
7.1
Background
The Intel Advanced+ Boot Block Stacked chip scale package combines the features of the
Advanced+ Boot Block flash memory architecture with a low-power SRAM to achieve an overall
reduction in system board space. This enables applications to integrate security with simple
software and hardware configurations, while also combining the system SRAM and flash into one
common footprint. This section discusses how to take full advantage of the 3 Volt Advanced+ Boot
Block Stacked Chip Scale Package.
7.1.1
7.1.2
Flash + SRAM Footprint Integration
The Stacked Chip Scale Package memory solution can be used to replace a subset of the memory
subsystem within a design. Where a previous design may have used two separate footprints for
SRAM and Flash, you can now replace with the industry-standard I-ballout of the Stacked-CSP
device. This allows for an overall reduction in board space, which allows the design to integrate
both the flash and the SRAM into one component.
Advanced+ Boot Block Flash Memory Features
Advanced+ Boot Block adds the following new features to Intel Advanced Boot Block
architecture:
• Instant, individual block locking provides software/hardware controlled, independent locking/
unlocking of any block with zero latency to protect code and data.
• A 128-bit Protection Register enables system security implementations.
• Improved 12 V production programming simplifies the system configuration required to
implement 12 V fast programming.
• Common Flash Interface (CFI) provides component information on the chip to allow software-
independent device upgrades.
For more information on specific advantages of the Advanced+ Boot Block Flash Memory, please
see AP-658 Designing with the Advanced+ Boot Block Flash Memory Architecture.
7.2
Flash Control Considerations
The flash device is protected against accidental block erasure or programming during power
transitions. Power supply sequencing is not required, since the device is indifferent as to which
power supply, F-VPP or F-VCC, powers-up first. Example flash power supply configurations are
shown in Figure 12, “Example Power Supply Configurations” on page 42.
Datasheet
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INTEL [ INTEL ]
