3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
5.8
Flash Reset Operations
Figure 8. AC Waveform: Reset Operation
V
IH
RP# (P)
tPHQV
tPHWL
tPHEL
VIL
t PLPH
(A) Reset during Read Mode
Abort
Complete
t PLRH
tPHQV
tPHWL
tPHEL
VIH
VIL
RP# (P)
t PLPH
t PLPH
t PLRH
<
(B) Reset during Program or Block Erase,
Abort Deep
Complete Power-
tPHQV
tPHWL
tPHEL
Down
t PLRH
VIH
VIL
RP# (P)
t PLPH
(C) Reset Program or Block Erase,
>
t PLPH t PLRH
Table 16. Reset Specifications(1)
F-V 2.7 V – 3.3 V
CC
Symbol
Parameter
Note
Unit
Min
Max
F-RP# Low to Reset during Read (If F-RP# is tied
t
2,4
100
ns
PLPH
to V , this specification is not applicable)
CC
t
t
F-RP# Low to Reset during Block Erase
F-RP# Low to Reset during Program
3,4
3,4
22
12
µs
µs
PLRH1
PLRH2
NOTES:
1. See Section 2.1.4, “Flash Reset” on page 13 for a full description of these conditions.
2. If t is < 100 ns the device may still reset but this is not guaranteed.
PLPH
3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will complete
within 100 ns.
4. Sampled, but not 100% tested.
34
Datasheet
INTEL [ INTEL ]
