BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
A block erase operation erases one of the device’s
64-Kbyte blocks typically within second
the WSM is performing a block erase, program, or
lock-bit configuration operation. RY/BY#-high
1
(5 V VCC, 12 V VPP), independent of other blocks.
Each block can be independently erased 100,000
times (1.6 million block erases per device). A block
erase suspend operation allows system software to
suspend block erase to read data from or write data
to any other block.
indicates that the WSM is ready for a new
command, block erase is suspended (and program
is inactive), program is suspended, or the device is
in deep power-down mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
Data is programmed in byte increments typically
within 6 µs (5 V VCC, 12 V VPP). A program
suspend operation permits system software to read
data or execute code from any other flash memory
array location.
5 V VCC
.
When CE# and RP# pins are at VCC
,
the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are
To protect programmed data, each block can be
locked. This block locking mechanism uses
a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
valid. Likewise, the device has a wake time (tPHEL
)
from RP#-high until writes to the CUI are
recognized.
1.3
Pinout and Pin Description
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package) and
40-bump µBGA* CSP (28F008SC and 28F016SC
only). Pinouts are shown in Figures 2, 3 and 4.
6
PRELIMINARY
INTEL [ INTEL ]
