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PA28F016SC-120 参数 Datasheet PDF下载

PA28F016SC-120图片预览
型号: PA28F016SC-120
PDF下载: 下载PDF文件 查看货源
内容描述: 字节宽SmartVoltage FlashFile⑩ Memory系列4 ,8和16 MBIT [BYTE-WIDE SmartVoltage FlashFile⑩ MEMORY FAMILY 4, 8, AND 16 MBIT]
分类和应用:
文件页数/大小: 42 页 / 723 K
品牌: INTEL [ INTEL ]
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY  
E
2.0 PRINCIPLES OF OPERATION  
1FFFFF  
The byte-wide SmartVoltage FlashFile memories  
1F0000  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
64-Kbyte Block  
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64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
64-Kbyte Block  
include an on-chip WSM to manage block erase,  
1EFFFF  
1E0000  
program, and lock-bit configuration functions. It  
1DFFFF  
allows for: 100% TTL-level control inputs, fixed  
1D0000  
power supplies during block erasure, program, and  
lock-bit configuration, and minimal processor  
overhead with RAM-like interface timings.  
1CFFFF  
1C0000  
1BFFFF  
1B0000  
1AFFFF  
1A0000  
19FFFF  
After initial device power-up or return from deep  
power-down mode (see Bus Operations), the  
device defaults to read array mode. Manipulation of  
external memory control pins allow array read,  
190000  
18FFFF  
180000  
17FFFF  
standby, and output disable operations.  
170000  
16FFFF  
160000  
Status register and identifier codes can be  
15FFFF  
accessed through the CUI independent of the VPP  
150000  
14FFFF  
voltage. High voltage on VPP enables successful  
140000  
block erasure, program, and lock-bit configuration.  
13FFFF  
All functions associated with altering memory  
130000  
12FFFF  
contents—block  
erase,  
program,  
lock-bit  
120000  
11FFFF  
configuration, status, and identifier codes—are  
accessed via the CUI and verified through the  
status register.  
110000  
10FFFF  
100000  
0FFFFF  
16-Mbit  
Commands are written using standard micro-  
processor write timings. The CUI contents serve as  
input to the WSM that controls block erase,  
program, and lock-bit configuration operations. The  
internal algorithms are regulated by the WSM,  
including pulse repetition, internal verification, and  
margining of data. Addresses and data are  
internally latched during write cycles. Writing the  
appropriate command outputs array data, accesses  
the identifier codes, or outputs status register data.  
0F0000  
0EFFFF  
0E0000  
0DFFFF  
0D0000  
0CFFFF  
0C0000  
0BFFFF  
0B0000  
0AFFFF  
0A0000  
09FFFF  
090000  
08FFFF  
8-Mbit  
8
080000  
07FFFF  
Interface software that initiates and polls progress  
of block erase, program, and lock-bit configuration  
can be stored in any block. This code is copied to  
and executed from system RAM during flash  
memory updates. After successful completion,  
reads are again possible via the Read Array  
command. Block erase suspend allows system  
software to suspend a block erase to read or write  
data from any other block. Program suspend allows  
system software to suspend a program to read data  
from any other flash memory array location.  
7
070000  
06FFFF  
6
060000  
05FFFF  
5
050000  
04FFFF  
4
040000  
03FFFF  
4-Mbit  
3
030000  
02FFFF  
2
020000  
01FFFF  
1
010000  
00FFFF  
0
000000  
Figure 5. Memory Map  
12  
PRELIMINARY  
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