28F640L30, 28F128L30, 28F256L30
Appendix G Ordering Information for S-CSP Package
Figure 43 shows the decoder for the 1.8 Volt Intel StrataFlash® wireless memory in Quad+ ballout
products.
Figure 43. Decoder for 1.8 Volt Intel StrataFlash® Wireless Memory (L30) in Quad+ Ballout
R D 4 8 F 3 0 0 0 L 0 Y B Q 0
Package
Device Details
RD = Intel® Stacked Chip Scale
0 = Original version of the
Package
products (refer to the latest
version of thedatasheet for
details).
NZ = Intel® Ultra-Thin Stacked Chip
Scale Package
Product Line Designator
48F = Flash Memory Only
Pinout Indicator
Q= Quad+ ballout
Flash Density
Parameter Location
B = Bottom Parameter
T = Top Par ameter
0 = No die
3 = 128-Mbit
4 = 256-Mbit
Voltage
Product Family
Y = 1.8 Volt Core and I/O
L = 1.8 Volt Intel StrataFlash® Wireless Flash Memory
0 = No Die
Z = 3 Volt I/O, 1.8 Volt Core
Table 28. Valid Combinations for S-CSP Package
I/O
128-Mbit
256-Mbit
RD48F3000L0ZTQ0
RD48F3000L0ZBQ0
NZ48F4000L0ZTQ0
NZ48F4000L0ZBQ0
3.0 V I/O
Datasheet
99
INTEL [ INTEL ]
