Low Power Features
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin (see Section 2.1.2.5). While
the processor is in the Sleep state, the SLP# pin must be de-asserted if another
asynchronous FSB event needs to occur.
2.1.2.5
Deep Sleep State
The Deep Sleep state is entered through assertion of the DPSLP# pin while in the
Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform
level power savings. BCLK stop/restart timings on appropriate chipset-based platforms
with the CK505 clock chip are as follows:
•
Deep Sleep entry: the system clock chip may stop/tri-state BCLK within 2 BCLKs
of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
•
Deep Sleep exit: the system clock chip must start toggling BCLK within 10 BCLK
periods within DPSLP# de-assertion.
To re-enter the Sleep state, the DPSLP# pin must be de-asserted. BCLK can be re-
started after DPSLP# de-assertion as described above. A period of 15 microseconds
(to allow for PLL stabilization) must occur before the processor can be considered to
be in the Sleep state. Once in the Sleep state, the SLP# pin must be de-asserted to
re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep
state, it will not respond to interrupts or snoop transactions. Any transition on an
input signal before the processor has returned to Stop-Grant state will result in
unpredictable behavior.
2.1.2.6
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but further reduces core
voltage levels. One of the potential lower core voltage levels is achieved by entering
the base Deeper Sleep state. The Deeper Sleep state is entered through assertion of
the DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level
is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of
Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of
the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely
shut down. Refer to Section 2.1.2.6.1 for further details on reducing the L2 cache and
entering Intel Enhanced Deeper Sleep state.
In response to entering Deeper Sleep, the processor drives the VID code
corresponding to the Deeper Sleep core voltage on the VID [6:0] pins.
Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP#
de-assertion when the core requests a package state other than C4 or the core
requests a processor performance state other than the lowest operating point.
2.1.2.6.1 Intel Enhanced Deeper Sleep State
Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power
saving capabilities by allowing the processor to further reduce core voltage once the
Datasheet
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INTEL [ INTEL ]
