Low Power Features
L2 cache has been reduced to zero ways and completely shut down. The following
events occur when the processor enters Intel Enhanced Deeper Sleep state:
•
The processor issues a P_LVL4 I/O read or an MWAIT(C4) instruction and then
progressively reduces the L2 cache to zero.
•
The processor drives the VID code corresponding to the Intel Enhanced Deeper
Sleep state core voltage on the VID [6:0] pins.
2.2
Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following
conditions:
•
The C0 timer that tracks continuous residency in the Normal package state, has
not expired. This timer is cleared during the first entry into Deeper Sleep to allow
consecutive Deeper Sleep entries to shrink the L2 cache as needed.
•
The FSB speed to processor core speed ratio is below the predefined L2 shrink
threshold.
If the FSB speed to processor core speed ratio is above the predefined L2 shrink
threshold, then L2 cache expansion will be requested. If the ratio is zero, then the
ratio will not be taken into account for Dynamic Cache Sizing decisions.
Upon STPCLK# de-assertion, the core exiting Intel Enhanced Deeper Sleep state will
expand the L2 cache to two ways and invalidate previously disabled cache ways. If the
L2 cache reduction conditions stated above still exist when the core returns to C4 then
package enters Intel Enhanced Deeper Sleep state, then the L2 will be shrunk to zero
again. If the core requests a processor performance state resulting in a higher ratio
than the predefined L2 shrink threshold, the C0 timer expires, then the whole L2 will
be expanded upon the next interrupt event.
L2 cache shrink prevention may be enabled as needed on occasion through an
MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not
enter Intel Enhanced Deeper Sleep state since the L2 cache remains valid and in full
size.
16
Datasheet
INTEL [ INTEL ]
