Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
Figure 1. LXT9763 Block Diagram
RESET
VCC
GND
Global Functions
CFG<2:0>
Pwr Supply
Management /
Mode Select
Logic
ADD<4:0>
MDIO
MDC
MDINT
REFCLK
Clock
Generator
Register Set
+
Manchester
10
TX_ENn
TXDn_<3:0>
TX_ERn
TP
Driver
Encoder
OSP
™
Pulse
TPFOP n
TPFON n
Parallel/Serial
Converter
Scrambler
& Encoder
-
100
TP / Fiber
Out
Shaper
+
TX_CLKn
ECL
Driver
Auto
Negotiation
-
Register
Set
ED/CFGn_<3:0>
COLn
OSP
™
Adaptive EQ with
BaseLine Wander
Cancellation
Collision
Detect
+
Media
Select
Clock
Generator
100TX
100FX
10BT
-
+
RX_CLKn
RXDn_<3:0>
RXDVn
TPFIP n
TPFIN n
Manchester
Decoder
TP / Fiber
In
Serial to
Parallel
Converter
10
OSP
™
Slicer
-
+
Decoder &
Descrambler
Carrier Sense
Data Valid
100
CRSn
Error Detect
RX_ERn
-
Per-Port Functions
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
Datasheet
9
INTEL [ INTEL ]
